TLK3131_15 Datasheet, PDF (43/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 2-48. JC_CLOCK_MUX_CONTROL
BIT(s)
37120.15:14
37120.13:12
37120.11:10
37120.9:8
37120.7:6
37120.5:4
ADDRESS: 0x9100
DEFAULT: 0x3FF0
NAME
DESCRIPTION
REF_SEL[1:0]
Jitter Cleaner Reference clock select control
00 = Selects differential REFCLKP/N as jitter cleaner clock input
01 = Selects CMOS REFCLK as jitter cleaner clock input
10 = Selects recovered clock as jitter cleaner clock input
11 = Reserved
RXB_SEL[1:0]
Jitter Cleaner RXBYTECLK select control
00 = Selects RXB_DIV divider output clock as RXBYTECLK
01 = Selects recovered clock as RXBYTECLK
10 = Selects CMOS REFCLK as RXBYTECLK
11 = Selects differential REFCLKP/N as RXBYTECLK
TX_SEL[1:0]
Jitter Cleaner SERDES TX Reference clock input select control
00 = Selects jitter cleaner output clock as TX SERDES reference clock input
01 = Selects recovered clock as TX SERDES reference clock input
10 = Selects CMOS REFCLK as TX SERDES reference clock input
11 = Selects differential REFCLKP/N as TX SERDES reference clock input
RX_SEL[1:0]
Jitter Cleaner SERDES RX Reference clock input select control
00 = Selects jitter cleaner output clock as RX SERDES reference clock input
01 = Selects recovered clock as RX SERDES reference clock input (Not Recommended)
10 = Selects CMOS REFCLK as RX SERDES reference clock input
11 = Selects differential REFCLKP/N as RX SERDES reference clock input
DEL_SEL[1:0]
Delay stopwatch clock input select control
00 = Selects delay clock divider output clock as delay stopwatch clock input
01 = Selects recovered clock as delay stopwatch clock input
10 = Selects CMOS REFCLK as delay stopwatch clock input
11 = Selects differential REFCLKP/N as delay stopwatch clock input
HSTL_SEL[1:0]
HSTL VTP 2x clock divider input select control
00 = Selects HSTL DIV clock output as HSTL VTP 2x clock divider input
01 = Selects recovered clock as HSTL VTP 2x clock divider input
10 = Selects CMOS REFCLK as HSTL VTP 2x clock divider input
11 = Selects differential REFCLKP/N as HSTL VTP 2x clock divider input
ACCESS
RW
RW
RW
RW
RW
RW
Table 2-49. JC_VTP_CLK_DIV_CONTROL
BIT(s)
37121.14:8
37121.6:0
ADDRESS: 0x9101
DEFAULT: 0x0E06
NAME
DESCRIPTION
HSTL_DIV[6:0]
HSTL Output Divider 1 Value. See Figure 1-2. This value is the divider value for the
clock which runs the HSTL impedance compensation controller. The target output
frequency for the impedance controller clock is 40 MHz. If the jitter cleaner is not
enabled, this value is not used.
Legal programmed values are greater than or equal to 6
HSTL_DIV2[6:0]
HSTL Output Divider 2 Value. See Figure 1-2. This value is the divider value for the
HSTL impedance compensation controller. The target output frequency for this
clock is 40 MHz. When the jitter cleaner (HSTL_DIV1) is used, this value should be
provisioned to 6 decimal. When the jitter cleaner (HSTL_DIV1) is not used, this
divider value should be provisioned according to the following equation:
Value = (Parallel Output Byte Clock Frequency / 40 MHz)
Legal programmed values are 1, and greater than or equal to 4
ACCESS
RW
RW
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