TLK3131_15 Datasheet, PDF (65/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 3-8. Jitter Cleaner Related Pins
SIGNAL
REFCLKP/
REFCLKN
VDDA_VCO
VSSA_VCO
VDDA_CP
VSSA_CP
VDD_CML
VSS_CML
VDD_PLL
VSS_PLL
VCO_TL_TST
TST_OUT
CP_OUT
VTUNE
LOCATION
G1
F1
F4
E2
G3
G4
H1
G2
E4
E1
H4
E3
F3
F2
TYPE
I
P
G
P
G
P
G
P
G
Analog Input
Analog
Input/Output
Analog Output
Analog Input
DESCRIPTION
Differential Reference Clock Inputs
By default, the differential reference clock (REFCLKP/N) is selected.
This default value may be changed by a mdio register (37120.15:14).
Must Be Externally AC Coupled
REFCLKP – DPECL REFCLK P Input
REFCLKN – DPECL REFCLK N Input
Acceptable input frequency range is 50 MHz → 375 MHz.
Jitter performance is optimal when using the differential REFCLK input.
Jitter Cleaner – VCO Supply – 1.2 V
Jitter Cleaner Ground
Jitter Cleaner – Charge Pump – 1.2 V
Jitter Cleaner Ground
Jitter Cleaner – REFCLKP/N Input Supply – 1.2 V
Jitter Cleaner Ground
Jitter Cleaner Digital Power (1.2 V)
Jitter Cleaner Ground
VCO Testability Input. This signal should be grounded in the application.
Jitter Cleaner Testability Pin. This signal should be left open (unconnected) in the
application.
Charge Pump Output. If the internal Jitter Cleaner PLL is used, this signal should be
connected to the input of the external loop filter (See Figure B-1). If the internal Jitter
Cleaner PLL is not used, this node should be left open (unconnected).
LC VCO Bias Voltage. This signal should be connected to the output of the external
loop filter if the Jitter Cleaner PLL is used (Figure B-1). If the internal Jitter Cleaner
PLL is not used, this node should be grounded.
1
2
A
DGND
RXD_3
B
RXD_4
RXD_6
C
VDDQ
RXD_7
D
VDDO
SPEED1
E
VSS_PLL
VSSA_VCO
F REFCLKN
VTUNE
G REFCLKP
VSS_CML
H VDD_CML
REFCLK
J
TESTEN
CODE
K
GPO4
GPO0
L PRBS_EN
PRTAD2
M
PRTAD1
RST_N
3
VDDQ
RXD_5
RES1
DGND
TST_OUT
CP_OUT
VDDA_CP
VDDO
DVDD
VDDT
TDN0
AVDD
4
RXCLK_0
VDDQ
DGND
DVDD
VDD_PLL
VDDA_VCO
VSSA_CP
VCO_TL_TST
ENABLE
AGND
TDP0
AGND
5
RXD_2
DGND
RXD_0
VDDQ
DGND
DGND
DGND
DGND
AVDD
VDDR
AVDD
VDDD
6
RXD_1
RXC_0
RXC_4
DVDD
DGND
DGND
DGND
DGND
AGND
VDDT
AGND
AMUX0
7
VPP
VPP
DGND
VDDQ
DGND
DGND
DGND
DGND
AVDD
DVDD
AVDD
VDDD
8
VREF2
TXD_3
TXC_4
DVDD
DGND
DGND
DGND
DGND
AVDD
AGND
RDP0
AGND
9
RES4
VDDQ
TXD_5
VDDQ
DVDD
DGND
GPO1
DVDD
AGND
VDDT
RDN0
VDDR
Figure 3-1. Device Pinout Diagram – (Top View)
10
TXD_0
TXD_6
TXD_1
TXD_4
VDDQ
GPO2
GPO3
SLOOP
PRTAD4
AVDD
AGND
AMUX1
11
DGND
TXC_0
DGND
TXD_2
TXCLK_0
TDO
VDDO
SPEED0
TMS
PLOOP
PRTAD3
VDDD
12
TXD_7
VDDQ
RES3
VREF1
MDIO
VDDM
MDC
TCK
TDI
TRST_N
GPI1
PRTAD0
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