TLK3131_15 Datasheet, PDF (27/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
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SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
2.7.11 Parallel Interface Clocking Modes
The TLK3131 supports source centered timing and source aligned DDR timing on the parallel receive
output bus. TLK3131 also supports rising edge aligned and falling edge aligned SDR timing on the parallel
receive output bus. See Figure 2-17 for more details.
RXCLK
Source Centered (DDR)
RXD
RXC
t_SETUP
t_HOLD
Data
t_SETUP
t_HOLD
Data
Source Aligned (DDR)
RXD
RXC
Data
Falling Edge Aligned (SDR)
RXD
RXC
Data
Data
Data
Data
Rising Edge Aligned (SDR)
RXD
RXC
Data
Data
Figure 2-17. Receive Interface Timing – Source Centered/Aligned
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