TLK3131_15 Datasheet, PDF (61/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 3-2. JTAG Signals
SIGNAL
TDI
TDO
TMS
TCK
TRST_N
LOCATION
J12
F11
J11
H12
K12
VOLTAGE
VDDO
VDDO
VDDO
VDDO
VDDO
TYPE
DESCRIPTION
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Input Data. TDI is used to serially shift test data and test instructions
into the device during the operation of the test port.
2.5 V LVCMOS
Output
JTAG Output Data. TDO is used to serially shift test data and test
instructions out of the device during operation of the test port. When the JTAG
port is not in use, TDO is in a high impedance state.
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Mode Select. TMS is used to control the state of the internal test-port
controller.
2.5 V LVCMOS JTAG Clock. TCK is used to clock state information and test data into and out
Input
of the device during the operation of the test port.
2.5 V LVCMOS
Input (Internal
Pullup)
JTAG Test Reset. TRST_N is used to reset the JTAG logic into system
operational mode.
Table 3-3. MDIO Related Signals
SIGNAL
MDC
MDIO
PRTAD[4:
0]
REFCLK
LOCATION
G12
E12
J10
L11
L2
M1
M12
H2
VOLTAGE
VDDM
VDDM
VDDO
VDDO
TYPE
1.2 V OR 2.5 V
LVCMOS Input
1.2 V OR 2.5 V
LVCMOS Input/
Output
2.5 V LVCMOS
Input
2.5 V LVCMOS
Input
DESCRIPTION
Management Interface Clock This clock is used to sample the MDIO signal.
Management Interface Data This bidirectional data line for MDIO Port is
sampled on the rising edge of MDC.
THIS SIGNAL MUST BE EXTERNALLY PULLED UP TO VDDM. Consult
IEEE802.3 Clause 22/45 for an appropriate resistance value.
Port Address Used to select Port ID in Clause 22 MDIO modes.
PRTAD[4:1] selects a block of two sequential Clause 22 port addresses.
Each channel (second channel datapath is not pinned out) is implemented as
a different port address, and can be accessed by setting the appropriate port
address field within the Clause 22 MDIO transaction.
PRTAD[0] is not used functionally, but is needed for device testability with
other devices in the family of products.
Channel 0 responds to port address 0 within the block of two port addresses.
Channel 1 (datapath not usable) responds to port address 1 within the block
of two port addresses.
Single Ended Reference Clock Single ended reference clock input. By
default, the differential reference clock (REFCLKP/N) is selected. This default
value may be changed by a mdio register (37120.15:14). The acceptable
input frequency range on this input signal is 50 MHz → 150 MHz.
Jitter performance is optimal when using the differential REFCLK input.
Copyright © 2008–2009, Texas Instruments Incorporated
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Device Reset Requirements/Procedure
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