TLK3131_15 Datasheet, PDF (37/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 2-24. PHY_TEST_PATTERN_COUNTER
BIT(s)
22.15:0
ADDRESS: 0x16
DEFAULT: 0xFFFD
NAME
DESCRIPTION
Fixed Test Pattern This counter reflects error count for high, Mixed, and Low Frequency test patterns. Counter
Error Counter
increments for each received character that has an error. Counter clears upon read.
ACCESS
COR
Table 2-25. PHY_CRPAT_PATTERN_COUNTER_1⁽¹⁾
BIT(s)
23.15:0
ADDRESS: 0x17
DEFAULT: 0xFFFF
NAME
DESCRIPTION
CRPAT Error
counter[31:16]
This counter reflects MSW part of error count for CRPAT Frequency test pattern. Counter
increments for each received character that has an error. Counter clears upon read.
ACCESS
COR
(1) User has to make sure that register 23 is read first and then register 24. If user reads register 24 before reading register 23, then the
count value read through register 24 may not be correct.
Table 2-26. PHY_CRPAT_PATTERN_COUNTER_2⁽¹⁾
BIT(s)
24.15:0
ADDRESS: 0x18
DEFAULT: 0xFFFD
NAME
DESCRIPTION
CRPAT Error
counter[15:0]
This counter reflects LSW part of error count for CRPAT Frequency test pattern. Counter
increments for each received character that has an error. Counter clears upon read.
ACCESS
COR
(1) User has to make sure that register 23 is read first and then register 24. If user reads register 24 before reading register 23, then the
count value read through register 24 may not be correct.
Table 2-27. PHY_TEST_MODE_CONTROL
BIT(s)
27.15
27.14:12
ADDRESS: 0x1B
DEFAULT: 0x7000
NAME
DESCRIPTION
Reserved
Reserved, This value always reads zero.
Test Mux Select
Mux control to select debug signals onto test mux data pins. For TI test purposes only
ACCESS
RW/SC
RW
BIT(s)
28.15
28.13
28:12
Table 2-28. PHY_CHANNEL_STATUS
ADDRESS: 0x1C
DEFAULT: 0x0000
NAME
DESCRIPTION
Signal Detect
When high, indicates that the SERDES detected valid signal.
Encoder Invalid Code
Word
When high, indicates that the 1000Base-X encoder received an invalid control word.
Decoder Invalid Code
Word
When high, indicates that the 1000Base-X decoder received an invalid code word.
ACCESS
RO/LL
RO/LH
Table 2-29. PHY_PRBS_HIGH_SPEED_TEST_COUNTER
BIT(s)
29.15:0
ADDRESS: 0x1D
DEFAULT: 0xFFFD
NAME
DESCRIPTION
PRBS High Speed
Test Counter
This counter reflects errors for PRBS (2^7) test pattern verification . Counter increments
by one for each received character that has error. This counter saturates at 16’hffff.
When read, it resets to zero and continues to count.
ACCESS
COR
BIT(s)
30.15:0
Table 2-30. PHY_EXT_ADDRESS_CONTROL
ADDRESS: 0x1E
DEFAULT: 0x0000
NAME
DESCRIPTION
Ext address control
This register should be written with the extended register address to be written/read.
Contents of address written in this register can be accessed from Reg 31 (0x1F).
ACCESS
RW
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Detailed Description
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