TLK3131_15 Datasheet, PDF (2/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
Contents
1 Introduction ........................................................................................................................ 9
1.1 Features ...................................................................................................................... 9
1.2 Pin Out ....................................................................................................................... 9
1.3 Description ................................................................................................................. 10
2 Detailed Description .......................................................................................................... 11
2.1 Clocking Modes ............................................................................................................ 11
2.2 Operating Frequency Range ............................................................................................. 12
2.3 CPRI Latency Support .................................................................................................... 12
2.4 Powerdown Mode ......................................................................................................... 12
2.5 Application Examples ..................................................................................................... 12
2.6 Device Operation Modes ................................................................................................. 16
2.7 Parallel Interface Modes - Detailed Description ....................................................................... 17
2.7.1 RGMII Mode (Reduced Gigabit Media Independent Interface) ........................................... 17
2.7.2 RTBI Mode (Reduced Ten Bit Interface) .................................................................... 18
2.7.3 TBI Mode (Ten Bit Interface) .................................................................................. 19
2.7.4 GMII Mode (Gigabit Media Independent Interface) ........................................................ 20
2.7.5 EBI Mode (Eight Bit Interface) ................................................................................ 21
2.7.6 REBI Mode (Reduced Eight Bit Interface) ................................................................... 22
2.7.7 NBI Mode (Nine Bit Interface Mode) ......................................................................... 23
2.7.8 RNBI Mode (Reduced Nine Bit Interface) ................................................................... 24
2.7.9 TBID Mode (Ten Bit Interface DDR) ......................................................................... 25
2.7.10 NBID Mode (Nine Bit Interface DDR) ........................................................................ 26
2.7.11 Parallel Interface Clocking Modes ............................................................................ 27
2.7.12 Parallel to Serial ................................................................................................ 28
2.7.13 Serial to Parallel ................................................................................................ 28
2.7.14 High Speed CML Output ....................................................................................... 28
2.7.15 High Speed Receiver .......................................................................................... 29
2.7.16 Loopback ........................................................................................................ 30
2.7.17 Link Test Functions ............................................................................................. 30
2.7.18 MDIO Management Interface ................................................................................. 30
2.7.19 MDIO Protocol Timing ......................................................................................... 31
2.7.20 Clause 22 Indirect Addressing ................................................................................ 31
2.8 PROGRAMMERS REFERENCE ........................................................................................ 33
2.9 Top Level Programmers Reference ..................................................................................... 38
3 Device Reset Requirements/Procedure ................................................................................ 53
3.1 Gigabit Ethernet Mode (RGMII) ......................................................................................... 53
3.2 JITTER TEST PATTERN GENERATION AND VERIFICATION PROCEDURES ................................ 56
3.3 PRBS Test Generation and Verification Procedures ................................................................. 58
3.4 Signal Pin Description .................................................................................................... 60
4 Electrical Specifications ..................................................................................................... 66
4.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 66
4.2 RECOMMENDED OPERATING CONDITIONS ....................................................................... 66
4.3 REFERENCE CLOCK TIMING REQUIREMENTS (REFCLKP/N) .................................................. 67
4.4 REFERENCE CLOCK ELECTRICAL CHARACTERISTICS (REFCLKP/N) ....................................... 67
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Contents
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