TLK3131_15 Datasheet, PDF (42/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 2-44. SERDES_RX1_STATUS
BIT(s)
36884.3:0
ADDRESS: 0x9014
NAME
Reserved
Reserved
DESCRIPTION
DEFAULT: 0x0000
Table 2-45. SERDES_TX0_STATUS⁽¹⁾
ADDRESS: 0x9017
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
36887.0
TX CH 0 TESTFAIL
When HIGH, indicates an error occurred during test pattern verification
for SERDES TX CH 0.
(1) Above status bits are only for Receive CH 1.
Table 2-46. SERDES_TX1_STATUS
BIT(s)
36888.0
ADDRESS: 0x9018
NAME
Reserved
Reserved
DESCRIPTION
DEFAULT: 0x0000
BIT(s)
36891.4
36891.0
Table 2-47. SERDES_PLL_STATUS
ADDRESS: 0x901B
DEFAULT: 0x0000
NAME
DESCRIPTION
PLL_LOCK_RX 1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES RX macro
PLL_LOCK_TX 1 = Indicates PLL is locked within 10ppm of REFCLKP/N in SERDES TX macro
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ACCESS
RO
ACCESS
RO
ACCESS
RO
ACCESS
RO/LL
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