TLK3131_15 Datasheet, PDF (73/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
4.14 HSTL Output Switching Characteristics (DDR Timing Mode Only)
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
t_setup RXDATA setup prior to RXCLK
transition high or low
Source Centered, See Figure 4-5.
Note: C_load = 10 pF, using timing reference of
VDDQ/2
0.15 ×
t_period
t_hold RXDATA hold after RXCLK transition Source Centered, See Figure 4-5.
high or low
Note: C_load = 10 pF, using timing reference of
VDDQ/2
0.15 ×
t_period
T_duty RXCLK Duty Cycle
Source Centered and Source Aligned.
Note: C_load = 10 pF, using timing reference of
VDDQ/2.
45%
t_period
T_freq
T_pd
RXCLK Period
RXCLK Frequency
RXCLK rising or falling to RXDATA
valid.
Source Centered and Source Aligned
Source Centered and Source Aligned
Source Aligned, See Figure 4-6.
Note: C_load = 10 pF, using timing reference of
VDDQ/2
6.25
60 ⁽²⁾
–0.10 ×
t_period
(1) In TBID/NBID Modes Only, the maximum allowed RXCLK period is 33.33 ns.
(2) In TBID/NBID Modes Only, the minimum allowed RXCLK frequency is 30 MHz.
NOM
MAX UNIT
ps
ps
55%
16.67 ⁽¹⁾
160
+0.10 ×
t_period
ns
MHz
ps
RXCLK
t_PERIOD
V_OH(ac)
VDDQ/2
V_OL(ac)
t_SETUP
t_HOLD
t_SETUP
t_HOLD
V_OH(ac)
RXDATA VDDQ/2
V_OL(ac)
Figure 4-5. HSTL (DDR Timing Mode Only) Source Centered Output Timing Requirements
RXCLK
V_OH(ac)
RXDATA VDDQ/2
V_OL(ac)
T_pd
T_pd
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-6. HSTL (DDR Timing Mode Only) Source Aligned Output Timing Requirements
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