TLK3131_15 Datasheet, PDF (62/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
Table 3-4. Parallel Data Pins
SIGNAL
TXCLK_0
TXD_[7:0]
TXC_[4,0]
RXCLK_0
RXD_[7:0]
RXC_[4,0]
LOCATION
E11
A12
B10
C9
D10
B8
D11
C10
A10
C8
B11
A4
C2
B2
B3
B1
A2
A5
A6
C5
C6
B6
VOLTAGE
VDDQ/ VREF1/2
VDDQ/ VREF1/2
VDDQ/ VREF1/2
VDDQ
VDDQ
VDDQ
TYPE
DESCRIPTION
1.5/1.8 V
HSTL Input
Transmit Data Clock (Parallel I/F) This is the parallel side input clock.
1.5/1.8 V
HSTL Input
Transmit Data Pins Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
1.5/1.8 V
HSTL Input
Transmit Data Control Parallel Control inputs.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
1.5/1.8 V
HSTL
Output
Receive Data Clock This signal is the parallel side output clock.
1.5/1.8 V
HSTL
Output
Receive Data Pins Parallel interface data pins.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
1.5/1.8 V
HSTL
Output
Receive Data Control Control inputs.
See the following tables for functionality per application mode:
Table 2-3 RGMII - Lane To Functional Pin Mapping
Table 2-4 RTBI - Lane To Functional Pin Mapping
Table 2-5 TBI - Lane To Functional Pin Mapping
Table 2-6 GMII - Lane To Functional Pin Mapping
Table 2-7 EBI - Lane To Functional Pin Mapping
Table 2-8 REBI - Lane To Functional Pin Mapping
Table 2-9 NBI - Lane To Functional Pin Mapping
Table 2-10 RNBI - Lane To Functional Pin Mapping
Table 2-11 TBID - Lane To Functional Pin Mapping
Table 2-12 NBID - Lane To Functional Pin Mapping
62
Device Reset Requirements/Procedure
Submit Documentation Feedback
Product Folder Link(s): TLK3131
Copyright © 2008–2009, Texas Instruments Incorporated