TLK3131_15 Datasheet, PDF (44/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 2-50. JC_DELAY_STOPWATCH_CLK_DIV_CONTROL
BIT(s)
37122.14:8
37122.2:1
37122.0
ADDRESS: 0x9102
DEFAULT: 0x0600
NAME
DESCRIPTION
DEL_DIV[6:0]
Delay Measurement Clock Output Divider Value. See Figure 1-2. Controls the clock
divider for the delay stop watch function. This value should be provisioned to
decimal 6.This value is only used when the delay calculator circuit is enabled.
Legal programmed values are greater than or equal to 6
Delay stop watch
lane select[1:0]
Lane select to enable comma monitor. Valid only when 37122:0 is “1”
00 = Comma monitor enabled
01 = Reserved
10 = Reserved
11 = Reserved
Delay stop watch
clock enable
When set, enables Delay stop watch clock
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Table 2-51. JC_DELAY_STOPWATCH_COUNTER
ADDRESS: 0x9103
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
37123.15:0
Delay stop watch
counter[15:0]
Delay Counter. This value represents the latency in number of clock cycles. This
counter resets on read and will return 16’h0000 if its read before rx comma is
received. If latency is more than 16’hFFFF clock cycles then this counter returns
16’hFFFF.
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Table 2-52. JC_REFCLK_FB_DIV_CONTROL
ADDRESS: 0x9104
DEFAULT: 0x018E
BIT(s)
NAME
DESCRIPTION
37124.15 REFDIV_EN
1 = Enables Reference clock divider
0 = Disables Reference clock divider
37124.14:8 REF_DIV[0:6]
Controls the clock divider value for the reference clock. See Figure 1-2, and
Appendix A for provisioning details
Note: REF_DIV[6:0] = 37124.8:14.
(Example: To program REF_DIV to decimal value 4, 14:8 needs to be set to
7’b0010000)
37124.7 FBDIV_EN
1 = Enables Feedback divider
0 = Disables feedback divider
37124.6:0 FB_DIV[6:0]
Controls the feedback divider value
See Figure 1-2, and Appendix A for provisioning details.
Note: JC_CHARGE_PUMP_ CONTROL (37126) needs to be set accordingly
based on FB_DIV range. Refer Table 2-55: Charge Pump Control Setting
(CP_CTRL)
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Table 2-53. JC_RXB_OUTPUT_CLK_DIV_CONTROL
ADDRESS: 0x9105
DEFAULT: 0x0E8E
BIT(s)
NAME
DESCRIPTION
37125.14:8 RXB_DIV[6:0]
Receive Byte Clock Output Divider Value. This divider value is always provisioned with the
same value as RXTX_DIV[6:0]. See Figure 1-2, and Appendix A for provisioning details. This
value is only used when the jitter cleaner is used to source the receive parallel interface
output clock. Legal programmed values are greater than or equal to 6
37125.7 OUTDIV_EN
1 = Enables output divider (RXTX_DIV)
0 = Disables output divider
RX/TX SERDES Output Divider Value
37125.6:0 RXTX_DIV[6:0] See Figure 1-2, and Appendix A for provisioning details Legal programmed values are
greater than or equal to 6
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