TLK3131_15 Datasheet, PDF (41/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
Table 2-41. SERDES_TEST_CONFIG_TX⁽¹⁾
ADDRESS: 0x9011
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
36881.10:8
Reserved
Reserved for TI test.
36881.7:6
LOOPBACK_TX
00 = Disabled
01 = Pad loopback. For TI purposes only
10 = Inner loopback (CML driver disabled)
11 = Inner loopback (CML driver enabled)
36881.5:4
CLKBYPASS_TX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKT
11 = Refclk observe (Reserved. For TI purposes only)
36881.3
ENRXPATT_TX
0 – Disables test pattern verification in SERDES TX macro.
1 – Enables test pattern verification in SERDES TX macro.
36881.2
ENTXPATT_TX
0 – Disables test pattern generation in SERDES TX macro.
1 – Enables test pattern generation in SERDES TX macro.
36881.1:0
TESTPATT_TX
Valid when ENTXPATT_TX, ENRXPATT_TX, ENTEST_TX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 2⁷ – 1 PRBS pattern
11 = 2²³ – 1 PRBS pattern
(1) Above control bits are only for vendor testing only. Customer should leave them at their default values
Table 2-42. SERDES_TEST_CONFIG_RX⁽¹⁾
ACCESS
RW
RW
RW
RW
RW
RW
ADDRESS: 0x9012
DEFAULT: 0x0000
BIT(s)
NAME
DESCRIPTION
36882.10:8
Reserved
Reserved for TI test.
36882.7:6
LOOPBACK_RX
00 = Disabled
01 = Pad loopback. For TI purposes only
10 = Inner loopback (CML driver disabled)
11 = Inner loopback (CML driver enabled)
36882.5:4
CLKBYPASS_RX
PLL Bypass control in test mode
00 = No bypass
01 = Reserved
10 = Functional bypass. Macros run using TESCLKR
11 = Refclk observe (Reserved. For TI purposes only)
36882.3
ENRXPATT_RX
0 – Disables test pattern verification in SERDES RX macro.
1 – Enables test pattern verification in SERDES RX macro.
36882.2
ENTXPATT_RX
0 – Disables test pattern generation in SERDES RX macro.
1 – Enables test pattern generation in SERDES RX macro.
36882.1:0
TESTPATT_RX
Valid when ENTXPATT_RX, ENRXPATT_RX, ENTEST_RX are set
00 = Reserved (Default)
01 = Clock pattern (Half baud clock pattern with period of 2UI)
10 = 2⁷ – 1 PRBS pattern
11 = 2²³ – 1 PRBS pattern
(1) Above control bits are only for vendor testing only. Customer should leave them at their default values
Table 2-43. SERDES_RX0_STATUS⁽¹⁾
ACCESS
RW
RW
RW
RW
RW
R
BIT(s)
36883.3
36883.2
36883.1
36883.0
ADDRESS: 0x9013
DEFAULT: 0x0000
NAME
DESCRIPTION
LOSDTCT
When HIGH indicates Loss of Signal condition is detected for RX CH 0
ODDCG
LOW when SYNC is HIGH. After that toggles every cycle.
SYNC
When comma detection is enabled, this bit is HIGH when an aligned comma is received.
RX CH 0
TESTFAIL
When HIGH, indicates an error occurred during test pattern verification for SERDES RX CH 0.
This bit status is valid only when SERDES RX test pattern verification bits are set
(1) Above status bits are only for Receive CH 0.
ACCESS
RO
RO
RO
RO
Copyright © 2008–2009, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s): TLK3131
Detailed Description
41