TLK3131_15 Datasheet, PDF (59/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
• If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– Issue Datapath Reset:
• Write 1’b1 to 16.11
• Write 1’b0, then 1'b1, followed by 1'b0 to 37636.14
– GPO0 contains a real time output that when high indicates if the input PRBS pattern on
TD×0/RD×0 is errored.
• SERDES Macro 2⁷-1/2²³-1 PRBS Register Based Testing
– Reset Device:
• Issue a hard or soft reset (RST_N asserted –or– Write 1 to 0.15)
– Power down channel 1 per procedure in previous device initialization section.
– Select single ended or differential REFCLK input:
• If Single Ended REFCLK used – Write 2’b01 to 37120.15:14
• If Differential REFCLK used – Write 2’b00 to 37120.15:14
– Select SERDES TX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.11:10
• If Differential REFCLK used – Write 2’b11 to 37120.11:10
– Select SERDES RX Reference Clock Input:
• If Single Ended REFCLK used – Write 2’b10 to 37120.9:8
• If Differential REFCLK used – Write 2’b11 to 37120.9:8
– Ensure a legal reference clock operation frequency is selected based on Appendix A, and provision
control settings accordingly. It is also possible to use the Jitter Cleaner during these tests, and the
user should consult Appendix A for further Jitter Cleaner provisioning details.
– PRBS Selection:
• For PRBS 2⁷-1-
– Write 2’b10 36881.1:0.
– Write 2’b10 36882.1:0.
• For PRBS 2²³-1-
– Write 2’b11 36881.1:0.
– Write 2’b11 36882.1:0.
– Enable PRBS Generation:
• Write 1’b1 to 36881.2
• Write 1’b1 to 36874.1
– Enable PRBS Verification:
• Write 1’b1 to 36882.3
• Write 1’b1 to 36866.1
– Clear Counters:
• Read 38144.7:0 and discard the value.
– The pattern verification is now in progress
– Verify Error Free Operation (as many times as desired during the duration of the test period):
• Read 38144.7:0, and verify 8’h00 is read to confirm error free operation on TDx0/RDx0.
– GPO0 contains a real time output that when high indicates if the input PRBS pattern on TDx0/RDx0
Copyright © 2008–2009, Texas Instruments Incorporated
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Device Reset Requirements/Procedure
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