TLK3131_15 Datasheet, PDF (28/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
www.ti.com
The transmit input timing modes are shown in Figure 2-18. SDR/DDR input timing modes supported are
similar to those supported in the receive direction.
TXCLK
Source Centered (DDR)
TXD
TXC
t_SETUP
t_HOLD
Data
t_SETUP
t_HOLD
Data
Source Aligned (DDR)
TXD
TXC
Data
Falling Edge Aligned (Rising Edge Sampled) (SDR)
TXD
TXC
Data
Data
Data
Data
Rising Edge Aligned (Falling Edge Sampled) (SDR)
TXD
TXC
Data
Data
Figure 2-18. Transmit Interface Timing
2.7.12 Parallel to Serial
The parallel-to-serial shift register takes in data and converts it to a serial stream. The shift register is
clocked by the internally generated bit clock, which is 10 times the reference clock (REFCLKP/REFCLKN)
frequency. The least significant bit (LSB) is transmitted first.
2.7.13 Serial to Parallel
Serial data is received on the RDP/RDN pins. The interpolator and clock recovery circuit will lock to the
data stream if the clock to be recovered is within ±200 PPM of the internally generated bit rate clock. The
recovered clock is used to retime the input data stream. The serial data is then clocked into the
serial-to-parallel shift registers. If enabled, the 10-bit wide parallel data is then fed into 8b/10b decoders.
2.7.14 High Speed CML Output
The high speed data output driver is implemented using Current Mode Logic (CML) with integrated pull up
resistors, requiring no external components. The line can be directly coupled or AC coupled. Under many
circumstances, AC coupling is desirable.
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