TLK3131_15 Datasheet, PDF (75/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
www.ti.com
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
4.16 HSTL (DDR Timing Mode Only) Input Timing Requirements
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN NOM⁽¹⁾
t_setup
TXDATA setup prior to Source Centered. See Figure 4-9.
TXCLK transition high Note: Input timing reference of VDDQ/2, with ±1 ns/V
or low
rise time on all input signals.
0.075 × t_period
TXDATA hold after
Source Centered. See Figure 4-9.
t_hold TXCLK transition high Note: Input timing reference of VDDQ/2, with ±1 ns/V 0.075 × t_period
or low
rise time on all input signals.
t_duty TXCLK Duty Cycle
Source Centered
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
40%
t_duty TXCLK Duty Cycle
Source Aligned
Note: Input timing reference of VDDQ/2, with ±1 ns/V
rise time on all input signals.
45%
t_period TXCLK Period
Tfreq TXCLK Frequency
Source Centered and Aligned.
Source Centered and Aligned.
6.25
60 ⁽³⁾
T_skew
TXCLK rising or falling
to TXDATA valid.
Source Aligned. See Figure 4-10.
Note: Input timing reference of VDDQ/2, with ±1 ns/V
–0.175 × t_period
(4)
rise time on all input signals.
(1) All typical values are at 25°C and with a nominal supply.
(2) In TBID/NBID Modes Only, the maximum allowed TXCLK period is 33.33 ns.
(3) In TBID/NBID Modes Only, the minimum allowed TXCLK frequency is 30 MHz.
(4) In TBID/NBID Modes, when the TXCLK is in the 30 → 60 MHz range, this parameter becomes -0.10 × t_period
(5) In TBID/NBID Modes, when the TXCLK is in the 30→ 60 MHz range, this parameter becomes +0.10 × t_period
MAX UNIT
ps
ps
60%
55%
16.67 ⁽²⁾
160
ns
MHz
+0.175 ×
t_period ⁽⁵⁾
ps
TXCLK
t_PERIOD
V_IH(ac)
VDDQ/2
V_IL(ac)
t_SETUP
t_HOLD
t_SETUP
t_HOLD
V_IH(ac)
TXDATA VDDQ/2
V_IL(ac)
Figure 4-9. HSTL (DDR Timing Mode Only) Source Centered Data Input Timing Requirements
TXCLK
TXDATA
V_OH(ac)
VDDQ/2
V_OL(ac)
Tskew
Tskew
V_OH(ac)
VDDQ/2
V_OL(ac)
Figure 4-10. HSTL (DDR Timing Mode Only) Source Aligned Data Input Timing Requirements
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