TLK3131_15 Datasheet, PDF (8/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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3-3 MDIO Related Signals ........................................................................................................... 61
3-4 Parallel Data Pins ................................................................................................................ 62
3-5 Serial Side Data/Clock Pins..................................................................................................... 63
3-6 Miscellaneous Pins............................................................................................................... 63
3-7 Voltage Supply and Reference Pins ........................................................................................... 64
3-8 Jitter Cleaner Related Pins...................................................................................................... 65
4-1 Parallel Interface – Valid Signal Operational Mode Definitions ............................................................ 72
4-2 TLK3131 Application Mode –vs– Interface Timing Mode Support ........................................................ 79
4-3 Worst Case Device Power Dissipation ........................................................................................ 81
A-1 Reference Clock Selection – Gigabit Ethernet Mode........................................................................ 82
A-2 Reference Clock Selection – 1X/2X Fibre Channel Mode .................................................................. 83
A-3 Reference Clock Selection – OBSAI Mode ................................................................................... 83
A-4 Reference Clock Selection – CPRI Mode..................................................................................... 84
A-5 Reference Clock Selection – 9/10 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00) ................................. 84
A-6 Reference Clock Selection – 9/10 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01) ................................ 85
A-7 Reference Clock Selection – 9/10 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10) ............................ 85
A-8 Reference Clock Selection – 8 Bit SERDES Mode – Full Rate (SPEED[1:0] = 00)..................................... 86
A-9 Reference Clock Selection – 8 Bit SERDES Mode – Half Rate (SPEED[1:0] = 01) .................................... 86
A-10 Reference Clock Selection – 8 Bit SERDES Mode – Quarter Rate (SPEED[1:0] = 10) ................................ 86
C-1 Device Mode Configuration ..................................................................................................... 98
C-2 Device Test Mode Pin Configuration .......................................................................................... 98
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