TLK3131_15 Datasheet, PDF (12/102 Pages) Texas Instruments – Single Channel Multi-Rate Transceiver

TLK3131
SLLS957A – DECEMBER 2008 – REVISED DECEMBER 2009
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2.2 Operating Frequency Range
The TLK3131 is optimized for operation at a serial data rate of 600 Mbit/s through 3.75 Gbit/s. The
external differential (optionally single ended) reference clock has a large operating frequency range
allowing support for many different applications. The reference clock frequency must be within ±200 PPM
of the incoming serial data rate, and have less than 40ps of jitter. The following table shows a summary of
frequency ranges supported. For more details, see Appendix A. The transmit parallel input clock must be
frequency locked (0 ppm) to the supplied REFCLK frequency.
Table 2-1. Supported Protocol Rates and REFCLK Values
PROTOCOL
1G Ethernet
1X/2X Fibre Channel
OBSAI
CPRI
Generic TBI
Generic RTBI
Generic NBID/TBID
Refclk (MHz)
62.5/125/250
53.125/106.25/212.5
76.8/153.6/307.2
61.44/122.88/245.76
50 → 375 MHz
50 → 375 MHz
50 → 375 MHz
LINE RATE (Gbps)
1.25
2.125
1.0625
3.072
1.536
0.768
2.4576
1.2288
0.6144
0.600 → 3.75
0.600 → 1.6
0.600 → 3.2
2.3 CPRI Latency Support
The TLK3131 has a round trip latency measurement capability to support its use in CPRI applications.
When enabled, the TLK3131 will measure the elapsed time from the transmission of a K28.5 code in a
CPRI frame until the reception of a K28.5 code in the receive path. This measurement result may be read
through an MDIO readable register. The measurement has an accuracy of ±4 ns with the Jitter Cleaner
PLL enabled, and an accuracy of ± two parallel byte clock periods if the Jitter Cleaner PLL is disabled.
2.4 Powerdown Mode
The TLK3131 (through the ENABLE pin and through register control) is capable of going into a low power
quiescent state. In this state, all analog and digital circuitry is disabled.
2.5 Application Examples
TLK3131 supports many different application modes. Detailed register settings per application mode are
shown in Table 2-2. The following application diagrams do not show all possible applications, and are
intended only to illustrate the flexibility of the device.
Figure 2-1 shows the TLK3131 in a single channel SERDES Application. The 1000Base-X PCS layer can
be enabled or disabled. Note that the 8B/10B encoder/decoder functions can either be turned on or turned
off. When turned off, either 5 or 10 bits (DDR/SDR) of data is accepted from and presented to the parallel
side. When the 8B/10B encoder/decoder functions are enabled, 1 bit of control and 8 bits of data are
accepted from and presented to the parallel side using the standardized (R)GMII control characters.
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Detailed Description
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