LM3S5R36_13 Datasheet, PDF (977/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Table 22-2. Signals by Pin Number (continued)
Pin Number
Pin Name
Pin Type Buffer Type^a Description
PA7
I/O
TTL
GPIO port A bit 7.
CAN0Tx
O
TTL
CAN module 0 transmit.
CCP3
I/O
TTL
Capture/Compare/PWM 3.
26
CCP4
I/O
TTL
Capture/Compare/PWM 4.
I2C1SDA
I/O
OD
I²C module 1 data.
PWM1
O
TTL
PWM 1. This signal is controlled by PWM Generator 0.
PWM5
O
TTL
PWM 5. This signal is controlled by PWM Generator 2.
PB3
I/O
TTL
GPIO port B bit 3.
Fault0
27
Fault3
I
TTL
PWM Fault 0.
I
TTL
PWM Fault 3.
I2C0SDA
I/O
OD
I²C module 0 data.
28
VDD
-
Power Positive supply for I/O and some logic.
29
GND
-
Power Ground reference for logic and I/O pins.
30
OSC0
I
Analog Main oscillator crystal input or an external clock reference input.
31
OSC1
O
Analog Main oscillator crystal output. Leave unconnected when using a
single-ended clock source.
32
WAKE
I
TTL
An external input that brings the processor out of Hibernate mode
when asserted.
33
HIB
O
OD
An output that indicates the processor is in Hibernate mode.
XOSC0
34
I
Analog Hibernation module oscillator crystal input or an external clock
reference input. Note that this is either a 4.194304-MHz crystal or
a 32.768-kHz oscillator for the Hibernation module RTC. See the
CLKSEL bit in the HIBCTL register.
35
XOSC1
O
Analog Hibernation module oscillator crystal output. Leave unconnected
when using a single-ended clock source.
36
GND
-
Power Ground reference for logic and I/O pins.
VBAT
37
-
Power Power source for the Hibernation module. It is normally connected
to the positive terminal of a battery and serves as the battery
backup/Hibernation module power-source supply.
VDDC
38
-
Power Positive supply for most of the logic function, including the
processor core and most peripherals. The voltage on this pin is
1.3 V and is supplied by the on-chip LDO. The VDDC pins should
only be connected to the LDO pin and an external capacitor as
specified in .
39
GND
-
Power Ground reference for logic and I/O pins.
40
RST
I
TTL
System reset input.
PB0
I/O
TTL
GPIO port B bit 0. This pin is not 5-V tolerant.
CCP0
I/O
TTL
Capture/Compare/PWM 0.
41
PWM2
O
TTL
PWM 2. This signal is controlled by PWM Generator 1.
U1Rx
I
TTL
UART module 1 receive. When in IrDA mode, this signal has IrDA
modulation.
October 06, 2012
977
Texas Instruments-Production Data