LM3S5R36_13 Datasheet, PDF (911/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Bit/Field
7:6
5:4
3:2
Name
ENUPD3
ENUPD2
ENUPD1
Type
R/W
R/W
R/W
Reset
0
Description
PWM3 Enable Update Mode
Value Description
0x0 Immediate
Writes to the PWM3EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1 Reserved
0x2 Locally Synchronized
Writes to the PWM3EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3 Globally Synchronized
Writes to the PWM3EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
0
PWM2 Enable Update Mode
Value Description
0x0 Immediate
Writes to the PWM2EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1 Reserved
0x2 Locally Synchronized
Writes to the PWM2EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3 Globally Synchronized
Writes to the PWM2EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
0
PWM1 Enable Update Mode
Value Description
0x0 Immediate
Writes to the PWM1EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1 Reserved
0x2 Locally Synchronized
Writes to the PWM1EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3 Globally Synchronized
Writes to the PWM1EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
October 06, 2012
911
Texas Instruments-Production Data