LM3S5R36_13 Datasheet, PDF (29/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Register 100: USB Receive Control and Status Endpoint 4 Low (USBRXCSRL4), offset 0x146 ............... 845
Register 101: USB Receive Control and Status Endpoint 5 Low (USBRXCSRL5), offset 0x156 ............... 845
Register 102: USB Receive Control and Status Endpoint 6 Low (USBRXCSRL6), offset 0x166 ............... 845
Register 103: USB Receive Control and Status Endpoint 7 Low (USBRXCSRL7), offset 0x176 ............... 845
Register 104: USB Receive Control and Status Endpoint 8 Low (USBRXCSRL8), offset 0x186 ............... 845
Register 105: USB Receive Control and Status Endpoint 9 Low (USBRXCSRL9), offset 0x196 ............... 845
Register 106: USB Receive Control and Status Endpoint 10 Low (USBRXCSRL10), offset 0x1A6 ........... 845
Register 107: USB Receive Control and Status Endpoint 11 Low (USBRXCSRL11), offset 0x1B6 ........... 845
Register 108: USB Receive Control and Status Endpoint 12 Low (USBRXCSRL12), offset 0x1C6 ........... 845
Register 109: USB Receive Control and Status Endpoint 13 Low (USBRXCSRL13), offset 0x1D6 ........... 845
Register 110: USB Receive Control and Status Endpoint 14 Low (USBRXCSRL14), offset 0x1E6 ........... 845
Register 111: USB Receive Control and Status Endpoint 15 Low (USBRXCSRL15), offset 0x1F6 ........... 845
Register 112: USB Receive Control and Status Endpoint 1 High (USBRXCSRH1), offset 0x117 .............. 848
Register 113: USB Receive Control and Status Endpoint 2 High (USBRXCSRH2), offset 0x127 .............. 848
Register 114: USB Receive Control and Status Endpoint 3 High (USBRXCSRH3), offset 0x137 .............. 848
Register 115: USB Receive Control and Status Endpoint 4 High (USBRXCSRH4), offset 0x147 .............. 848
Register 116: USB Receive Control and Status Endpoint 5 High (USBRXCSRH5), offset 0x157 .............. 848
Register 117: USB Receive Control and Status Endpoint 6 High (USBRXCSRH6), offset 0x167 .............. 848
Register 118: USB Receive Control and Status Endpoint 7 High (USBRXCSRH7), offset 0x177 .............. 848
Register 119: USB Receive Control and Status Endpoint 8 High (USBRXCSRH8), offset 0x187 .............. 848
Register 120: USB Receive Control and Status Endpoint 9 High (USBRXCSRH9), offset 0x197 .............. 848
Register 121: USB Receive Control and Status Endpoint 10 High (USBRXCSRH10), offset 0x1A7 .......... 848
Register 122: USB Receive Control and Status Endpoint 11 High (USBRXCSRH11), offset 0x1B7 .......... 848
Register 123: USB Receive Control and Status Endpoint 12 High (USBRXCSRH12), offset 0x1C7 ......... 848
Register 124: USB Receive Control and Status Endpoint 13 High (USBRXCSRH13), offset 0x1D7 ......... 848
Register 125: USB Receive Control and Status Endpoint 14 High (USBRXCSRH14), offset 0x1E7 .......... 848
Register 126: USB Receive Control and Status Endpoint 15 High (USBRXCSRH15), offset 0x1F7 .......... 848
Register 127: USB Receive Byte Count Endpoint 1 (USBRXCOUNT1), offset 0x118 .............................. 851
Register 128: USB Receive Byte Count Endpoint 2 (USBRXCOUNT2), offset 0x128 .............................. 851
Register 129: USB Receive Byte Count Endpoint 3 (USBRXCOUNT3), offset 0x138 .............................. 851
Register 130: USB Receive Byte Count Endpoint 4 (USBRXCOUNT4), offset 0x148 .............................. 851
Register 131: USB Receive Byte Count Endpoint 5 (USBRXCOUNT5), offset 0x158 .............................. 851
Register 132: USB Receive Byte Count Endpoint 6 (USBRXCOUNT6), offset 0x168 .............................. 851
Register 133: USB Receive Byte Count Endpoint 7 (USBRXCOUNT7), offset 0x178 .............................. 851
Register 134: USB Receive Byte Count Endpoint 8 (USBRXCOUNT8), offset 0x188 .............................. 851
Register 135: USB Receive Byte Count Endpoint 9 (USBRXCOUNT9), offset 0x198 .............................. 851
Register 136: USB Receive Byte Count Endpoint 10 (USBRXCOUNT10), offset 0x1A8 .......................... 851
Register 137: USB Receive Byte Count Endpoint 11 (USBRXCOUNT11), offset 0x1B8 ........................... 851
Register 138: USB Receive Byte Count Endpoint 12 (USBRXCOUNT12), offset 0x1C8 .......................... 851
Register 139: USB Receive Byte Count Endpoint 13 (USBRXCOUNT13), offset 0x1D8 .......................... 851
Register 140: USB Receive Byte Count Endpoint 14 (USBRXCOUNT14), offset 0x1E8 .......................... 851
Register 141: USB Receive Byte Count Endpoint 15 (USBRXCOUNT15), offset 0x1F8 .......................... 851
Register 142: USB Receive Double Packet Buffer Disable (USBRXDPKTBUFDIS), offset 0x340 ............. 853
Register 143: USB Transmit Double Packet Buffer Disable (USBTXDPKTBUFDIS), offset 0x342 ............ 855
Register 144: USB Device RESUME Raw Interrupt Status (USBDRRIS), offset 0x410 ............................ 857
Register 145: USB Device RESUME Interrupt Mask (USBDRIM), offset 0x414 ....................................... 858
Register 146: USB Device RESUME Interrupt Status and Clear (USBDRISC), offset 0x418 .................... 859
Register 147: USB DMA Select (USBDMASEL), offset 0x450 ................................................................ 860
October 06, 2012
29
Texas Instruments-Production Data