LM3S5R36_13 Datasheet, PDF (371/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
8.3.5
a. Process the newly received data in buffer A or signal the buffer processing code that buffer
A has data available.
b. Reprogram the primary channel control word at offset 0x88 according to Table
8-12 on page 370.
2. Read the alternate channel control word at offset 0x288 and check the XFERMODE field. If the
field is 0, this means buffer B is complete. If buffer B is complete, then:
a. Process the newly received data in buffer B or signal the buffer processing code that buffer
B has data available.
b. Reprogram the alternate channel control word at offset 0x288 according to Table
8-12 on page 370.
Configuring Channel Assignments
Channel assignments for each μDMA channel can be changed using the DMACHASGN register.
Each bit represents a μDMA channel. If the bit is set, then the secondary function is used for the
channel.
Refer to Table 8-1 on page 352 for channel assignments.
For example, to use SSI1 Receive on channel 8 instead of UART0, set bit 8 of the DMACHASGN
register.
8.4 Register Map
Table 8-13 on page 371 lists the μDMA channel control structures and registers. The channel control
structure shows the layout of one entry in the channel control table. The channel control table is
located in system memory, and the location is determined by the application, that is, the base
address is n/a (not applicable). In the table below, the offset for the channel control structures is the
offset from the entry in the channel control table. See “Channel Configuration” on page 354 and Table
8-3 on page 355 for a description of how the entries in the channel control table are located in memory.
The μDMA register addresses are given as a hexadecimal increment, relative to the μDMA base
address of 0x400F.F000. Note that the μDMA module clock must be enabled before the registers
can be programmed (see page 274). There must be a delay of 3 system clocks after the μDMA
module clock is enabled before any μDMA module registers are accessed.
Table 8-13. μDMA Register Map
Offset Name
Type
Reset
Description
μDMA Channel Control Structure (Offset from Channel Control Table Base)
0x000 DMASRCENDP
R/W
-
DMA Channel Source Address End Pointer
0x004 DMADSTENDP
R/W
-
DMA Channel Destination Address End Pointer
0x008 DMACHCTL
R/W
-
DMA Channel Control Word
μDMA Registers (Offset from μDMA Base Address)
0x000 DMASTAT
RO
0x001F.0000 DMA Status
0x004 DMACFG
WO
-
DMA Configuration
0x008 DMACTLBASE
R/W
0x0000.0000 DMA Channel Control Base Pointer
See
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October 06, 2012
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