LM3S5R36_13 Datasheet, PDF (37/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Table 1. Revision History (continued)
Date
December 2010
Revision
8832
Description
■ Information on Advanced Encryption Standard (AES) cryptography tables and Cyclic Redundancy
Check (CRC) error detection functionality was inadvertently omitted from some datasheets. This
has been added.
■ In APINT register, changed bit name from SYSRESETREQ to SYSRESREQ.
■ Added DEBUG (Debug Priority) bit field to SYSPRI3 register.
■ Clarified Flash memory caution.
■ Restructured the General-Purpose Timer chapter to combine duplicated text.
■ Combined High and Low bit fields in GPTMTAILR, GPTMTAMATCHR, GPTMTAR, GPTMTAV,
GPTMTBILR, GPTMTAMATCHR, GPTMTBR and GPTMTBV registers for compatibility with future
releases.
■ Removed mention of false-start bit detection in the UART chapter. This feature is not supported.
■ Added SSI master clock restriction that SSIClk cannot be faster than 25 MHz.
■ Changed I²C master and slave register base addresses and offsets to be relative to I²C module
base, so register base and offsets were changed for all I²C slave registers.
■ In Electrical Characteristics chapter:
– Added single-ended clock source input voltage values to "Recommended DC Operating
Conditions" table.
– Deleted Oscillation mode value from "MOSC Oscillator Input Characteristics" table.
– Added T_{VDD2_3} supply voltage parameter to "Reset Characteristics" table.
– Added "Power-On Reset and Voltage Parameters" timing diagram.
– Added t_{VDDRISE_HIB} supply voltage parameter to "Hibernation Module AC Characteristics" table.
– Added "VDD Ramp when Waking from Hibernation" timing diagram.
October 06, 2012
37
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