LM3S5R36_13 Datasheet, PDF (25/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
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Register 28:
Register 29:
UART LIN Timer (UARTLTIM), offset 0x098 ..................................................................... 652
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 653
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 654
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 655
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 656
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 657
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 658
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 659
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 660
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 661
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 662
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 663
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 664
Synchronous Serial Interface (SSI) ............................................................................................ 665
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 680
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 682
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 684
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 685
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 687
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 688
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 689
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 691
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 693
Register 10: SSI DMA Control (SSIDMACTL), offset 0x024 ................................................................. 694
Register 11: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 695
Register 12: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 696
Register 13: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 697
Register 14: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 698
Register 15: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 699
Register 16: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 700
Register 17: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 701
Register 18: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 702
Register 19: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 703
Register 20: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 704
Register 21: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 705
Register 22: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 706
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 707
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 723
Register 2: I²C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 724
Register 3: I²C Master Data (I2CMDR), offset 0x008 ......................................................................... 729
Register 4: I²C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 730
Register 5: I²C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 731
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
I²C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 732
I²C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 733
I²C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 734
I²C Master Configuration (I2CMCR), offset 0x020 ............................................................ 735
I²C Slave Own Address (I2CSOAR), offset 0x800 ............................................................ 736
October 06, 2012
25
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