LM3S5R36_13 Datasheet, PDF (92/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

The Cortex-M3 Processor
NRND: Not recommended for new designs.
2.4.5.2
2.4.6
When reading a word in the alias region, 0x0000.0000 indicates that the targeted bit in the bit-band
region is clear and 0x0000.0001 indicates that the targeted bit in the bit-band region is set.
Directly Accessing a Bit-Band Region
“Behavior of Memory Accesses” on page 88 describes the behavior of direct byte, halfword, or word
accesses to the bit-band regions.
Data Storage
The processor views memory as a linear collection of bytes numbered in ascending order from zero.
For example, bytes 0-3 hold the first stored word, and bytes 4-7 hold the second stored word. Data
is stored in little-endian format, with the least-significant byte (lsbyte) of a word stored at the
lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte.
Figure 2-5 on page 92 illustrates how data is stored.
Figure 2-5. Data Storage
Memory
7
0
Address A B0 lsbyte
Register
31 24 23 16 15 8 7
0
B3
B2
B1
B0
A+1 B1
A+2 B2
A+3 B3 msbyte
2.4.7
Synchronization Primitives
The Cortex-M3 instruction set includes pairs of synchronization primitives which provide a
non-blocking mechanism that a thread or process can use to obtain exclusive access to a memory
location. Software can use these primitives to perform a guaranteed read-modify-write memory
update sequence or for a semaphore mechanism.
A pair of synchronization primitives consists of:
■ A Load-Exclusive instruction, which is used to read the value of a memory location and requests
exclusive access to that location.
■ A Store-Exclusive instruction, which is used to attempt to write to the same memory location and
returns a status bit to a register. If this status bit is clear, it indicates that the thread or process
gained exclusive access to the memory and the write succeeds; if this status bit is set, it indicates
that the thread or process did not gain exclusive access to the memory and no write was
performed.
The pairs of Load-Exclusive and Store-Exclusive instructions are:
■ The word instructions LDREX and STREX
■ The halfword instructions LDREXH and STREXH
■ The byte instructions LDREXB and STREXB
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October 06, 2012
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