LM3S5R36_13 Datasheet, PDF (565/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Bit/Field
7:4
Name
EM1
Type
R/W
Reset
0x0
Description
SS1 Trigger Select
This field selects the trigger source for Sample Sequencer 1.
The valid configurations for this field are:
Value Event
0x0
Processor (default)
The trigger is initiated by setting the SSn bit in the ADCPSSI
register.
0x1
Analog Comparator 0
This trigger is configured by the Analog Comparator Control
0 (ACCTL0) register (page 872).
0x2
Analog Comparator 1
This trigger is configured by the Analog Comparator Control
1 (ACCTL1) register (page 872).
0x3
reserved
0x4
External (GPIO PB4)
This trigger is connected to the GPIO interrupt for PB4 (see
“ADC Trigger Source” on page 414).
0x5
Timer
In addition, the trigger must be enabled with the TnOTE bit
in the GPTMCTL register (page 480).
0x6
PWM0
The PWM generator 0 trigger can be configured with the
PWM0 Interrupt and Trigger Enable (PWM0INTEN) register
(page 918).
0x7
PWM1
The PWM generator 1 trigger can be configured with the
PWM1INTEN register (page 918).
0x8
PWM2
The PWM generator 2 trigger can be configured with the
PWM2INTEN register (page 918).
0x9
PWM3
The PWM generator 3 trigger can be configured with the
PWM3INTEN register (page 918).
0xA-0xE reserved
0xF
Always (continuously sample)
October 06, 2012
565
Texas Instruments-Production Data