LM3S5R36_13 Datasheet, PDF (11/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
List of Figures
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Stellaris LM3S5R36 Microcontroller High-Level Block Diagram ............................... 47
CPU Block Diagram ............................................................................................. 68
TPIU Block Diagram ............................................................................................ 69
Cortex-M3 Register Set ........................................................................................ 71
Bit-Band Mapping ................................................................................................ 91
Data Storage ....................................................................................................... 92
Vector Table ........................................................................................................ 98
Exception Stack Frame ...................................................................................... 100
SRD Use Example ............................................................................................. 114
JTAG Module Block Diagram .............................................................................. 175
Test Access Port State Machine ......................................................................... 178
IDCODE Register Format ................................................................................... 184
BYPASS Register Format ................................................................................... 184
Boundary Scan Register Format ......................................................................... 185
Basic RST Configuration .................................................................................... 189
External Circuitry to Extend Power-On Reset ....................................................... 189
Reset Circuit Controlled by Switch ...................................................................... 190
Power Architecture ............................................................................................ 193
Main Clock Tree ................................................................................................ 196
Hibernation Module Block Diagram ..................................................................... 288
Using a Crystal as the Hibernation Clock Source ................................................. 290
Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON
Mode ................................................................................................................ 291
Internal Memory Block Diagram .......................................................................... 313
μDMA Block Diagram ......................................................................................... 351
Example of Ping-Pong μDMA Transaction ........................................................... 357
Memory Scatter-Gather, Setup and Configuration ................................................ 359
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 360
Peripheral Scatter-Gather, Setup and Configuration ............................................. 362
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 363
Digital I/O Pads ................................................................................................. 411
Analog/Digital I/O Pads ...................................................................................... 412
GPIODATA Write Example ................................................................................. 413
GPIODATA Read Example ................................................................................. 413
GPTM Module Block Diagram ............................................................................ 460
Timer Daisy Chain ............................................................................................. 464
Input Edge-Count Mode Example ....................................................................... 466
16-Bit Input Edge-Time Mode Example ............................................................... 468
16-Bit PWM Mode Example ................................................................................ 469
WDT Module Block Diagram .............................................................................. 506
Implementation of Two ADC Blocks .................................................................... 531
ADC Module Block Diagram ............................................................................... 532
ADC Sample Phases ......................................................................................... 535
Doubling the ADC Sample Rate .......................................................................... 536
Skewed Sampling .............................................................................................. 536
Sample Averaging Example ............................................................................... 537
October 06, 2012
11
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