LM3S5R36_13 Datasheet, PDF (22/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
Register 26:
Register 27:
Register 28:
Register 29:
Register 30:
Register 31:
Register 32:
Register 33:
Register 34:
GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 423
GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 424
GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 425
GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 426
GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 427
GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 428
GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 430
GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 431
GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 432
GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 433
GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 434
GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 436
GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 438
GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 439
GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 441
GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 442
GPIO Analog Mode Select (GPIOAMSEL), offset 0x528 ................................................... 444
GPIO Port Control (GPIOPCTL), offset 0x52C ................................................................. 445
GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 447
GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 448
GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 449
GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 450
GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 451
GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 452
GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 453
GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 454
GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 455
GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 456
GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 457
GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 458
General-Purpose Timers ............................................................................................................. 459
Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 475
Register 2: GPTM Timer A Mode (GPTMTAMR), offset 0x004 ........................................................... 476
Register 3: GPTM Timer B Mode (GPTMTBMR), offset 0x008 ........................................................... 478
Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 480
Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 483
Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 485
Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 488
Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 491
Register 9: GPTM Timer A Interval Load (GPTMTAILR), offset 0x028 ................................................ 493
Register 10: GPTM Timer B Interval Load (GPTMTBILR), offset 0x02C ................................................ 494
Register 11: GPTM Timer A Match (GPTMTAMATCHR), offset 0x030 .................................................. 495
Register 12: GPTM Timer B Match (GPTMTBMATCHR), offset 0x034 ................................................. 496
Register 13: GPTM Timer A Prescale (GPTMTAPR), offset 0x038 ....................................................... 497
Register 14: GPTM Timer B Prescale (GPTMTBPR), offset 0x03C ...................................................... 498
Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 499
Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 500
Register 17: GPTM Timer A (GPTMTAR), offset 0x048 ....................................................................... 501
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October 06, 2012
Texas Instruments-Production Data