LM3S5R36_13 Datasheet, PDF (3/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Table of Contents
Revision History ............................................................................................................................. 33
About This Document .................................................................................................................... 43
Audience .............................................................................................................................................. 43
About This Manual ................................................................................................................................ 43
Related Documents ............................................................................................................................... 43
Documentation Conventions .................................................................................................................. 44
1
1.1
1.2
1.3
1.3.1
1.3.2
1.3.3
1.3.4
1.3.5
1.3.6
1.3.7
1.3.8
1.4
Architectural Overview .......................................................................................... 46
Overview ...................................................................................................................... 46
Target Applications ........................................................................................................ 48
Features ....................................................................................................................... 48
ARM Cortex-M3 Processor Core .................................................................................... 48
On-Chip Memory ........................................................................................................... 50
Serial Communications Peripherals ................................................................................ 51
System Integration ........................................................................................................ 55
Advanced Motion Control ............................................................................................... 61
Analog .......................................................................................................................... 63
JTAG and ARM Serial Wire Debug ................................................................................ 64
Packaging and Temperature .......................................................................................... 65
Hardware Details .......................................................................................................... 65
2
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.3
2.3.1
2.3.2
2.3.3
2.3.4
2.3.5
2.3.6
2.4
2.4.1
2.4.2
2.4.3
2.4.4
2.4.5
2.4.6
2.4.7
2.5
2.5.1
2.5.2
2.5.3
The Cortex-M3 Processor ...................................................................................... 66
Block Diagram .............................................................................................................. 67
Overview ...................................................................................................................... 68
System-Level Interface .................................................................................................. 68
Integrated Configurable Debug ...................................................................................... 68
Trace Port Interface Unit (TPIU) ..................................................................................... 69
Cortex-M3 System Component Details ........................................................................... 69
Programming Model ...................................................................................................... 70
Processor Mode and Privilege Levels for Software Execution ........................................... 70
Stacks .......................................................................................................................... 70
Register Map ................................................................................................................ 71
Register Descriptions .................................................................................................... 72
Exceptions and Interrupts .............................................................................................. 85
Data Types ................................................................................................................... 85
Memory Model .............................................................................................................. 85
Memory Regions, Types and Attributes ........................................................................... 87
Memory System Ordering of Memory Accesses .............................................................. 87
Behavior of Memory Accesses ....................................................................................... 88
Software Ordering of Memory Accesses ......................................................................... 88
Bit-Banding ................................................................................................................... 89
Data Storage ................................................................................................................ 92
Synchronization Primitives ............................................................................................. 92
Exception Model ........................................................................................................... 93
Exception States ........................................................................................................... 94
Exception Types ............................................................................................................ 94
Exception Handlers ....................................................................................................... 97
October 06, 2012
3
Texas Instruments-Production Data