LM3S5R36_13 Datasheet, PDF (619/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
The first thing to consider when programming the UART is the baud-rate divisor (BRD), because
the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using
the equation described in “Baud-Rate Generation” on page 612, the BRD can be calculated:
BRD = 20,000,000 / (16 * 115,200) = 10.8507
which means that the DIVINT field of the UARTIBRD register (see page 629) should be set to 10
decimal or 0xA. The value to be loaded into the UARTFBRD register (see page 630) is calculated
by the equation:
UARTFBRD[DIVFRAC] = integer(0.8507 * 64 + 0.5) = 54
With the BRD values in hand, the UART configuration is written to the module in the following order:
1. Disable the UART by clearing the UARTEN bit in the UARTCTL register.
2. Write the integer portion of the BRD to the UARTIBRD register.
3. Write the fractional portion of the BRD to the UARTFBRD register.
4. Write the desired serial parameters to the UARTLCRH register (in this case, a value of
0x0000.0060).
5. Optionally, configure the µDMA channel (see “Micro Direct Memory Access (μDMA)” on page 350)
and enable the DMA option(s) in the UARTDMACTL register.
6. Enable the UART by setting the UARTEN bit in the UARTCTL register.
13.5
Register Map
Table 13-2 on page 619 lists the UART registers. The offset listed is a hexadecimal increment to the
register’s address, relative to that UART’s base address:
■ UART0: 0x4000.C000
■ UART1: 0x4000.D000
■ UART2: 0x4000.E000
Note that the UART module clock must be enabled before the registers can be programmed (see
page 265). There must be a delay of 3 system clocks after the UART module clock is enabled before
any UART module registers are accessed.
Note: The UART must be disabled (see the UARTEN bit in the UARTCTL register on page 633)
before any of the control registers are reprogrammed. When the UART is disabled during
a TX or RX operation, the current transaction is completed prior to the UART stopping.
Table 13-2. UART Register Map
Offset Name
Type
0x000 UARTDR
R/W
0x004 UARTRSR/UARTECR R/W
0x018 UARTFR
RO
0x020 UARTILPR
R/W
0x024 UARTIBRD
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0090
0x0000.0000
0x0000.0000
Description
UART Data
UART Receive Status/Error Clear
UART Flag
UART IrDA Low-Power Register
UART Integer Baud-Rate Divisor
See
page
621
623
626
628
629
October 06, 2012
619
Texas Instruments-Production Data