LM3S5R36_13 Datasheet, PDF (33/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Revision History
The revision history table notes changes made between the indicated revisions of the LM3S5R36
data sheet.
Table 1. Revision History
Date
October 2012
Revision Description
13442.2549 ■ Marked LM3S5R36 device as not recommended for new designs (NRND). Device is in production
to support existing customers, but TI does not recommend using this part in a new design.
■ Clarified that all GPIO signals are 5-V tolerant when configured as inputs except for PB0 and PB1,
which are limited to 3.6 V.
■ In the Watchdog Timers chapter, added information on servicing the watchdog timer to the
Initialization and Configuration section.
■ In the General-Purpose Timers chapter, added note to the GPTMTnV registers that in 16-bit mode,
only the lower 16-bits of the register can be written with a new value. Writes to the prescaler bits
have no effect.
■ Corrected reset for the UART Raw Interrupt Status (UARTRIS) register.
■ In the USB chapter, removed reference to USB low-speed operation including deleting the USB
Low-Speed Last Transaction to End of Frame Timing (USBLSEOF) register and the FORCEFS
bit in the USB Test Mode (USBTEST) register. Low-speed operation is not valid in USB device-only
mode.
■ In the USB chapter, clarified that the USB PHY has internal termination resistors, and thus there is
no need for external resistors.
■ In the Electrical Characteristics chapter, added clarifying footnote to the GPIO Module Characteristics
table.
■ Additional minor data sheet clarifications and corrections.
January 2012
11425
■ In System Control chapter:
– Clarified that an external LDO cannot be used.
– Clarified system clock requirements when the ADC module is in operation.
– Added important note to write the RCC register before the RCC2 register.
■ In Hibernation chapter:
– Changed terminology from non-volatile memory to battery-backed memory.
– Numerous clarifications, including adding a section "System Implementation".
– Clarified Hibernation module register reset conditions.
■ In Internal Memory chapter, clarified programming and use of the non-volatile registers.
■ In GPIO chapter, corrected "GPIO Pins With Non-Zero Reset Values" table and added note that if
the same signal is assigned to two different GPIO port pins, the signal is assigned to the port with
the lowest letter.
■ In Timer chapter, clarified timer modes and interrupts.
■ In ADC chapter, added "ADC Input Equivalency Diagram".
■ In UART chapter, clarified interrupt behavior.
October 06, 2012
33
Texas Instruments-Production Data