LM3S5R36_13 Datasheet, PDF (722/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Inter-Integrated Circuit (I²C) Interface
Table 15-3. Inter-Integrated Circuit (I²C) Interface Register Map (continued)
Offset Name
0x018 I2CMMIS
0x01C I2CMICR
0x020 I2CMCR
I²C Slave
0x800 I2CSOAR
0x804 I2CSCSR
0x808 I2CSDR
0x80C I2CSIMR
0x810 I2CSRIS
0x814 I2CSMIS
0x818 I2CSICR
Type
RO
WO
R/W
Reset
0x0000.0000
0x0000.0000
0x0000.0000
Description
I2C Master Masked Interrupt Status
I2C Master Interrupt Clear
I2C Master Configuration
R/W
0x0000.0000 I2C Slave Own Address
RO
0x0000.0000 I2C Slave Control/Status
R/W
0x0000.0000 I2C Slave Data
R/W
0x0000.0000 I2C Slave Interrupt Mask
RO
0x0000.0000 I2C Slave Raw Interrupt Status
RO
0x0000.0000 I2C Slave Masked Interrupt Status
WO
0x0000.0000 I2C Slave Interrupt Clear
See
page
733
734
735
736
737
739
740
741
742
743
15.6
Register Descriptions (I²C Master)
The remainder of this section lists and describes the I²C master registers, in numerical order by
address offset.
722
October 06, 2012
Texas Instruments-Production Data