LM3S5R36_13 Datasheet, PDF (634/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Universal Asynchronous Receivers/Transmitters (UARTs)
Bit/Field
8
7
6
5
4
Name
TXE
LBE
LIN
HSE
EOT
Type
R/W
R/W
R/W
R/W
R/W
Reset
1
0
Description
UART Transmit Enable
Value Description
1 The transmit section of the UART is enabled.
0 The transmit section of the UART is disabled.
If the UART is disabled in the middle of a transmission, it completes the
current character before stopping.
Note: To enable transmission, the UARTEN bit must also be set.
UART Loop Back Enable
Value Description
1 The UnTx path is fed through the UnRx path.
0 Normal operation.
0
LIN Mode Enable
Value Description
1 The UART operates in LIN mode.
0 Normal operation.
0
High-Speed Enable
Value Description
0 The UART is clocked using the system clock divided by 16.
1 The UART is clocked using the system clock divided by 8.
Note:
System clock used is also dependent on the baud-rate divisor
configuration (see page 629) and page 630).
The state of this bit has no effect on clock generation in ISO
7816 smart card mode (the SMART bit is set).
0
End of Transmission
This bit determines the behavior of the TXRIS bit in the UARTRIS
register.
Value Description
1 The TXRIS bit is set only after all transmitted data, including
stop bits, have cleared the serializer.
0 The TXRIS bit is set when the transmit FIFO condition specified
in UARTIFLS is met.
634
October 06, 2012
Texas Instruments-Production Data