LM3S5R36_13 Datasheet, PDF (375/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Register 3: DMA Channel Control Word (DMACHCTL), offset 0x008
DMA Channel Control Word (DMACHCTL) is part of the Channel Control Structure and is used
to specify parameters of a μDMA transfer.
Note: The offset specified is from the base address of the control structure in system memory,
not the μDMA module base address.
DMA Channel Control Word (DMACHCTL)
Base n/a
Offset 0x008
Type R/W, reset -
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
DSTINC
DSTSIZE
SRCINC
SRCSIZE
reserved
ARBSIZE
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ARBSIZE
XFERSIZE
XFERMODE
Type R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit/Field
31:30
Name
DSTINC
Type
R/W
Reset
-
Description
Destination Address Increment
This field configures the destination address increment.
The address increment value must be equal or greater than the value
of the destination size (DSTSIZE).
Value Description
0x0 Byte
Increment by 8-bit locations
0x1 Half-word
Increment by 16-bit locations
0x2 Word
Increment by 32-bit locations
0x3 No increment
Address remains set to the value of the Destination Address
End Pointer (DMADSTENDP) for the channel
October 06, 2012
375
Texas Instruments-Production Data