LM3S5R36_13 Datasheet, PDF (9/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
19.3 Functional Description ................................................................................................. 877
19.3.1 PWM Timer ................................................................................................................. 877
19.3.2 PWM Comparators ...................................................................................................... 878
19.3.3 PWM Signal Generator ................................................................................................ 879
19.3.4 Dead-Band Generator ................................................................................................. 880
19.3.5 Interrupt/ADC-Trigger Selector ..................................................................................... 880
19.3.6 Synchronization Methods ............................................................................................ 881
19.3.7 Fault Conditions .......................................................................................................... 882
19.3.8 Output Control Block ................................................................................................... 882
19.4 Initialization and Configuration ..................................................................................... 883
19.5 Register Map .............................................................................................................. 884
19.6 Register Descriptions .................................................................................................. 887
20 Quadrature Encoder Interface (QEI) ................................................................... 950
20.1 Block Diagram ............................................................................................................ 950
20.2 Signal Description ....................................................................................................... 951
20.3 Functional Description ................................................................................................. 952
20.4 Initialization and Configuration ..................................................................................... 954
20.5 Register Map .............................................................................................................. 954
20.6 Register Descriptions .................................................................................................. 955
21 Pin Diagram .......................................................................................................... 972
22 Signal Tables ........................................................................................................ 973
22.1 Signals by Pin Number ................................................................................................ 974
22.2 Signals by Signal Name ............................................................................................... 980
22.3 Signals by Function, Except for GPIO ........................................................................... 986
22.4 GPIO Pins and Alternate Functions .............................................................................. 992
22.5 Possible Pin Assignments for Alternate Functions ......................................................... 993
22.6 Connections for Unused Signals ................................................................................... 994
23 Operating Characteristics ................................................................................... 996
24 Electrical Characteristics .................................................................................... 997
24.1 Maximum Ratings ....................................................................................................... 997
24.2 Recommended Operating Conditions ........................................................................... 997
24.3 Load Conditions .......................................................................................................... 998
24.4 JTAG and Boundary Scan ............................................................................................ 998
24.5 Power and Brown-Out ............................................................................................... 1000
24.6 Reset ........................................................................................................................ 1001
24.7 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 1002
24.8 Clocks ...................................................................................................................... 1002
24.8.1 PLL Specifications ..................................................................................................... 1002
24.8.2 PIOSC Specifications ................................................................................................ 1003
24.8.3 Internal 30-kHz Oscillator Specifications ..................................................................... 1003
24.8.4 Hibernation Clock Source Specifications ..................................................................... 1004
24.8.5 Main Oscillator Specifications ..................................................................................... 1004
24.8.6 System Clock Specification with ADC Operation .......................................................... 1005
24.8.7 System Clock Specification with USB Operation .......................................................... 1005
24.9 Sleep Modes ............................................................................................................. 1005
24.10 Hibernation Module ................................................................................................... 1006
24.11 Flash Memory ........................................................................................................... 1007
October 06, 2012
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