LM3S5R36_13 Datasheet, PDF (1024/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Register Quick Reference
NRND: Not recommended for new designs.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
FCIM, type R/W, offset 0x010, reset 0x0000.0000
FCMISC, type R/W1C, offset 0x014, reset 0x0000.0000
PMASK AMASK
FMC2, type R/W, offset 0x020, reset 0x0000.0000
FWBVAL, type R/W, offset 0x030, reset 0x0000.0000
FCTL, type R/W, offset 0x0F8, reset 0x0000.0000
WRKEY
FWB[n]
FWB[n]
PMISC AMISC
WRBUF
FWBn, type R/W, offset 0x100 - 0x17C, reset 0x0000.0000
Internal Memory
Memory Registers (System Control Offset)
Base 0x400F.E000
RMCTL, type R/W1C, offset 0x0F0, reset -
DATA
DATA
USDACK USDREQ
FMPRE0, type R/W, offset 0x130 and 0x200, reset 0xFFFF.FFFF
FMPPE0, type R/W, offset 0x134 and 0x400, reset 0xFFFF.FFFF
BOOTCFG, type R/W, offset 0x1D0, reset 0xFFFF.FFFE
NW
PORT
PIN
USER_REG0, type R/W, offset 0x1E0, reset 0xFFFF.FFFF
NW
USER_REG1, type R/W, offset 0x1E4, reset 0xFFFF.FFFF
NW
USER_REG2, type R/W, offset 0x1E8, reset 0xFFFF.FFFF
NW
USER_REG3, type R/W, offset 0x1EC, reset 0xFFFF.FFFF
NW
FMPRE1, type R/W, offset 0x204, reset 0xFFFF.FFFF
POL
FMPRE2, type R/W, offset 0x208, reset 0xFFFF.FFFF
READ_ENABLE
READ_ENABLE
PROG_ENABLE
PROG_ENABLE
EN
DATA
DATA
DATA
DATA
DATA
DATA
DATA
DATA
READ_ENABLE
READ_ENABLE
READ_ENABLE
READ_ENABLE
BA
DBG1 DBG0
1024
Texas Instruments-Production Data
October 06, 2012