LM3S5R36_13 Datasheet, PDF (7/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
12.3.3 Hardware Sample Averaging Circuit ............................................................................. 537
12.3.4 Analog-to-Digital Converter .......................................................................................... 537
12.3.5 Differential Sampling ................................................................................................... 540
12.3.6 Internal Temperature Sensor ........................................................................................ 543
12.3.7 Digital Comparator Unit ............................................................................................... 543
12.4 Initialization and Configuration ..................................................................................... 548
12.4.1 Module Initialization ..................................................................................................... 548
12.4.2 Sample Sequencer Configuration ................................................................................. 549
12.5 Register Map .............................................................................................................. 549
12.6 Register Descriptions .................................................................................................. 551
13 Universal Asynchronous Receivers/Transmitters (UARTs) ............................. 609
13.1 Block Diagram ............................................................................................................ 610
13.2 Signal Description ....................................................................................................... 610
13.3 Functional Description ................................................................................................. 611
13.3.1 Transmit/Receive Logic ............................................................................................... 611
13.3.2 Baud-Rate Generation ................................................................................................. 612
13.3.3 Data Transmission ...................................................................................................... 612
13.3.4 Serial IR (SIR) ............................................................................................................. 613
13.3.5 ISO 7816 Support ....................................................................................................... 614
13.3.6 LIN Support ................................................................................................................ 614
13.3.7 FIFO Operation ........................................................................................................... 616
13.3.8 Interrupts .................................................................................................................... 616
13.3.9 Loopback Operation .................................................................................................... 617
13.3.10 DMA Operation ........................................................................................................... 617
13.4 Initialization and Configuration ..................................................................................... 618
13.5 Register Map .............................................................................................................. 619
13.6 Register Descriptions .................................................................................................. 620
14 Synchronous Serial Interface (SSI) .................................................................... 665
14.1 Block Diagram ............................................................................................................ 666
14.2 Signal Description ....................................................................................................... 666
14.3 Functional Description ................................................................................................. 667
14.3.1 Bit Rate Generation ..................................................................................................... 667
14.3.2 FIFO Operation ........................................................................................................... 667
14.3.3 Interrupts .................................................................................................................... 668
14.3.4 Frame Formats ........................................................................................................... 669
14.3.5 DMA Operation ........................................................................................................... 676
14.4 Initialization and Configuration ..................................................................................... 677
14.5 Register Map .............................................................................................................. 678
14.6 Register Descriptions .................................................................................................. 679
15 Inter-Integrated Circuit (I²C) Interface ................................................................ 707
15.1 Block Diagram ............................................................................................................ 708
15.2 Signal Description ....................................................................................................... 708
15.3 Functional Description ................................................................................................. 708
15.3.1 I²C Bus Functional Overview ........................................................................................ 709
15.3.2 Available Speed Modes ............................................................................................... 711
15.3.3 Interrupts .................................................................................................................... 712
15.3.4 Loopback Operation .................................................................................................... 713
15.3.5 Command Sequence Flow Charts ................................................................................ 713
October 06, 2012
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