LM3S5R36_13 Datasheet, PDF (909/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Register 11: PWM Enable Update (PWMENUPD), offset 0x028
This register specifies when updates to the PWMnEN bit in the PWMENABLE register are performed.
The PWMnEN bit enables the pwmA' or pwmB' output to be passed to the microcontroller's pin.
Updates can be immediate or locally or globally synchronized to the next synchronous update.
PWM Enable Update (PWMENUPD)
PWM0 base: 0x4002.8000
Offset 0x028
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
Type
Reset
Type
Reset
RO
RO
0
0
15
14
ENUPD7
R/W
R/W
0
0
RO
RO
0
0
13
12
ENUPD6
R/W
R/W
0
0
RO
RO
0
0
11
10
ENUPD5
R/W
R/W
0
0
25
24
23
22
reserved
RO
RO
RO
RO
0
0
0
0
9
8
ENUPD4
R/W
R/W
0
0
7
6
ENUPD3
R/W
R/W
0
0
21
20
RO
RO
0
0
5
4
ENUPD2
R/W
R/W
0
0
19
18
RO
RO
0
0
3
2
ENUPD1
R/W
R/W
0
0
17
16
RO
RO
0
0
1
0
ENUPD0
R/W
R/W
0
0
Bit/Field
31:16
15:14
Name
reserved
ENUPD7
Type
RO
R/W
Reset
0x00
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
PWM7 Enable Update Mode
Value Description
0x0 Immediate
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator immediately.
0x1 Reserved
0x2 Locally Synchronized
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0.
0x3 Globally Synchronized
Writes to the PWM7EN bit in the PWMENABLE register are used
by the PWM generator the next time the counter is 0 after a
synchronous update has been requested through the PWM
Master Control (PWMCTL) register.
October 06, 2012
909
Texas Instruments-Production Data