LM3S5R36_13 Datasheet, PDF (12/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
Figure 12-7. ADC Input Equivalency Diagram ......................................................................... 538
Figure 12-8. Internal Voltage Conversion Result ..................................................................... 539
Figure 12-9. External Voltage Conversion Result .................................................................... 540
Figure 12-10. Differential Sampling Range, V_{IN_ODD} = 1.5 V ...................................................... 541
Figure 12-11. Differential Sampling Range, V_{IN_ODD} = 0.75 V .................................................... 542
Figure 12-12. Differential Sampling Range, V_{IN_ODD} = 2.25 V .................................................... 542
Figure 12-13. Internal Temperature Sensor Characteristic ......................................................... 543
Figure 12-14. Low-Band Operation (CIC=0x0 and/or CTC=0x0) ................................................ 546
Figure 12-15. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ................................................. 547
Figure 12-16. High-Band Operation (CIC=0x3 and/or CTC=0x3) ................................................ 548
Figure 13-1. UART Module Block Diagram ............................................................................. 610
Figure 13-2. UART Character Frame ..................................................................................... 611
Figure 13-3. IrDA Data Modulation ......................................................................................... 614
Figure 13-4. LIN Message ..................................................................................................... 615
Figure 13-5. LIN Synchronization Field ................................................................................... 616
Figure 14-1. SSI Module Block Diagram ................................................................................. 666
Figure 14-2. TI Synchronous Serial Frame Format (Single Transfer) ........................................ 669
Figure 14-3. TI Synchronous Serial Frame Format (Continuous Transfer) ................................ 670
Figure 14-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 .......................... 671
Figure 14-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .................. 671
Figure 14-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ......................................... 672
Figure 14-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............... 673
Figure 14-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 673
Figure 14-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 674
Figure 14-10. MICROWIRE Frame Format (Single Frame) ........................................................ 675
Figure 14-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 676
Figure 14-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 676
Figure 15-1. I²C Block Diagram ............................................................................................. 708
Figure 15-2. I²C Bus Configuration ........................................................................................ 709
Figure 15-3. START and STOP Conditions ............................................................................. 709
Figure 15-4. Complete Data Transfer with a 7-Bit Address ....................................................... 710
Figure 15-5. R/S Bit in First Byte ............................................................................................ 710
Figure 15-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 710
Figure 15-7. Master Single TRANSMIT .................................................................................. 714
Figure 15-8. Master Single RECEIVE ..................................................................................... 715
Figure 15-9. Master TRANSMIT with Repeated START ........................................................... 716
Figure 15-10. Master RECEIVE with Repeated START ............................................................. 717
Figure 15-11. Master RECEIVE with Repeated START after TRANSMIT with Repeated
START .............................................................................................................. 718
Figure 15-12. Master TRANSMIT with Repeated START after RECEIVE with Repeated
START .............................................................................................................. 719
Figure 15-13. Slave Command Sequence ................................................................................ 720
Figure 16-1. CAN Controller Block Diagram ............................................................................ 745
Figure 16-2. CAN Data/Remote Frame .................................................................................. 746
Figure 16-3. Message Objects in a FIFO Buffer ...................................................................... 755
Figure 16-4. CAN Bit Time .................................................................................................... 759
Figure 17-1. USB Module Block Diagram ............................................................................... 794
Figure 18-1. Analog Comparator Module Block Diagram ......................................................... 862
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October 06, 2012
Texas Instruments-Production Data