LM3S5R36_13 Datasheet, PDF (611/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Table 13-1. UART Signals (64LQFP) (continued)
Pin Name
Pin Number Pin Mux / Pin Pin Type Buffer Type^a Description
Assignment
U0Tx
18
PA1 (1)
O
TTL
UART module 0 transmit. When in IrDA mode, this
signal has IrDA modulation.
U1Rx
15
PC6 (5)
I
17
PA0 (9)
41
PB0 (5)
58
PB4 (7)
61
PD0 (5)
63
PD2 (1)
TTL
UART module 1 receive. When in IrDA mode, this
signal has IrDA modulation.
U1Tx
16
PC7 (5)
O
18
PA1 (9)
42
PB1 (5)
57
PB5 (7)
62
PD1 (5)
64
PD3 (1)
TTL
UART module 1 transmit. When in IrDA mode, this
signal has IrDA modulation.
U2Rx
58
PB4 (4)
I
61
PD0 (4)
TTL
UART module 2 receive. When in IrDA mode, this
signal has IrDA modulation.
U2Tx
8
PE4 (5)
O
62
PD1 (4)
TTL
UART module 2 transmit. When in IrDA mode, this
signal has IrDA modulation.
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
Each Stellaris UART performs the functions of parallel-to-serial and serial-to-parallel conversions.
It is similar in functionality to a 16C550 UART, but is not register compatible.
The UART is configured for transmit and/or receive via the TXE and RXE bits of the UART Control
(UARTCTL) register (see page 633). Transmit and receive are both enabled out of reset. Before any
control registers are programmed, the UART must be disabled by clearing the UARTEN bit in
UARTCTL. If the UART is disabled during a TX or RX operation, the current transaction is completed
prior to the UART stopping.
The UART module also includes a serial IR (SIR) encoder/decoder block that can be connected to
an infrared transceiver to implement an IrDA SIR physical layer. The SIR function is programmed
using the UARTCTL register.
13.3.1
Transmit/Receive Logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO.
The control logic outputs the serial bit stream beginning with a start bit and followed by the data bits
(LSB first), parity bit, and the stop bits according to the programmed configuration in the control
registers. See Figure 13-2 on page 611 for details.
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start
pulse has been detected. Overrun, parity, frame error checking, and line-break detection are also
performed, and their status accompanies the data that is written to the receive FIFO.
Figure 13-2. UART Character Frame
UnTX
1
0
n
Start
LSB
MSB
5-8 data bits
1-2
stop bits
Parity bit
if enabled
October 06, 2012
611
Texas Instruments-Production Data