LM3S5R36_13 Datasheet, PDF (712/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Inter-Integrated Circuit (I²C) Interface
Table 15-2 gives examples of the timer periods that should be used to generate SCL frequencies
based on various system clock frequencies.
Table 15-2. Examples of I²C Master Timer Period versus Speed Mode
System Clock
4 MHz
6 MHz
12.5 MHz
16.7 MHz
20 MHz
25 MHz
33 MHz
40 MHz
50 MHz
80 MHz
Timer Period
0x01
0x02
0x06
0x08
0x09
0x0C
0x10
0x13
0x18
0x27
Standard Mode
100 Kbps
100 Kbps
89 Kbps
93 Kbps
100 Kbps
96.2 Kbps
97.1 Kbps
100 Kbps
100 Kbps
100 Kbps
Timer Period
-
-
0x01
0x02
0x02
0x03
0x04
0x04
0x06
0x09
Fast Mode
-
-
312 Kbps
278 Kbps
333 Kbps
312 Kbps
330 Kbps
400 Kbps
357 Kbps
400 Kbps
15.3.3
Interrupts
The I²C can generate interrupts when the following conditions are observed:
■ Master transaction completed
■ Master arbitration lost
■ Master transaction error
■ Slave transaction received
■ Slave transaction requested
■ Stop condition on bus detected
■ Start condition on bus detected
The I²C master and I²C slave modules have separate interrupt signals. While both modules can
generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt
controller.
15.3.3.1
I²C Master Interrupts
The I²C master module generates an interrupt when a transaction completes (either transmit or
receive), when arbitration is lost, or when an error occurs during a transaction. To enable the I²C
master interrupt, software must set the IM bit in the I²C Master Interrupt Mask (I2CMIMR) register.
When an interrupt condition is met, software must check the ERROR and ARBLST bits in the I²C
Master Control/Status (I2CMCS) register to verify that an error didn't occur during the last transaction
and to ensure that arbitration has not been lost. An error condition is asserted if the last transaction
wasn't acknowledged by the slave. If an error is not detected and the master has not lost arbitration,
the application can proceed with the transfer. The interrupt is cleared by writing a 1 to the IC bit in
the I²C Master Interrupt Clear (I2CMICR) register.
If the application doesn't require the use of interrupts, the raw interrupt status is always visible via
the I²C Master Raw Interrupt Status (I2CMRIS) register.
712
October 06, 2012
Texas Instruments-Production Data