LM3S5R36_13 Datasheet, PDF (18/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
List of Registers
The Cortex-M3 Processor ............................................................................................................. 66
Register 1: Cortex General-Purpose Register 0 (R0) ........................................................................... 73
Register 2: Cortex General-Purpose Register 1 (R1) ........................................................................... 73
Register 3: Cortex General-Purpose Register 2 (R2) ........................................................................... 73
Register 4: Cortex General-Purpose Register 3 (R3) ........................................................................... 73
Register 5: Cortex General-Purpose Register 4 (R4) ........................................................................... 73
Register 6: Cortex General-Purpose Register 5 (R5) ........................................................................... 73
Register 7: Cortex General-Purpose Register 6 (R6) ........................................................................... 73
Register 8: Cortex General-Purpose Register 7 (R7) ........................................................................... 73
Register 9: Cortex General-Purpose Register 8 (R8) ........................................................................... 73
Register 10: Cortex General-Purpose Register 9 (R9) ........................................................................... 73
Register 11: Cortex General-Purpose Register 10 (R10) ....................................................................... 73
Register 12: Cortex General-Purpose Register 11 (R11) ........................................................................ 73
Register 13: Cortex General-Purpose Register 12 (R12) ....................................................................... 73
Register 14: Stack Pointer (SP) ........................................................................................................... 74
Register 15: Link Register (LR) ............................................................................................................ 75
Register 16: Program Counter (PC) ..................................................................................................... 76
Register 17: Program Status Register (PSR) ........................................................................................ 77
Register 18: Priority Mask Register (PRIMASK) .................................................................................... 81
Register 19: Fault Mask Register (FAULTMASK) .................................................................................. 82
Register 20: Base Priority Mask Register (BASEPRI) ............................................................................ 83
Register 21: Control Register (CONTROL) ........................................................................................... 84
Cortex-M3 Peripherals ................................................................................................................. 108
Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 ........................................... 119
Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 .............................................. 121
Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 ........................................... 122
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 .................................................................. 123
Register 5: Interrupt 32-54 Set Enable (EN1), offset 0x104 ................................................................ 124
Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 .............................................................. 125
Register 7: Interrupt 32-54 Clear Enable (DIS1), offset 0x184 ............................................................ 126
Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 ........................................................... 127
Register 9: Interrupt 32-54 Set Pending (PEND1), offset 0x204 ......................................................... 128
Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 ................................................... 129
Register 11: Interrupt 32-54 Clear Pending (UNPEND1), offset 0x284 .................................................. 130
Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 ............................................................. 131
Register 13: Interrupt 32-54 Active Bit (ACTIVE1), offset 0x304 ........................................................... 132
Register 14: Interrupt 0-3 Priority (PRI0), offset 0x400 ......................................................................... 133
Register 15: Interrupt 4-7 Priority (PRI1), offset 0x404 ......................................................................... 133
Register 16: Interrupt 8-11 Priority (PRI2), offset 0x408 ....................................................................... 133
Register 17: Interrupt 12-15 Priority (PRI3), offset 0x40C .................................................................... 133
Register 18: Interrupt 16-19 Priority (PRI4), offset 0x410 ..................................................................... 133
Register 19: Interrupt 20-23 Priority (PRI5), offset 0x414 ..................................................................... 133
Register 20: Interrupt 24-27 Priority (PRI6), offset 0x418 ..................................................................... 133
Register 21: Interrupt 28-31 Priority (PRI7), offset 0x41C .................................................................... 133
Register 22: Interrupt 32-35 Priority (PRI8), offset 0x420 ..................................................................... 133
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October 06, 2012
Texas Instruments-Production Data