LM3S5R36_13 Datasheet, PDF (5/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
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Hibernation Module .............................................................................................. 287
6.1 Block Diagram ............................................................................................................ 288
6.2 Signal Description ....................................................................................................... 288
6.3 Functional Description ................................................................................................. 289
6.3.1 Register Access Timing ............................................................................................... 289
6.3.2 Hibernation Clock Source ............................................................................................ 289
6.3.3 System Implementation ............................................................................................... 291
6.3.4 Battery Management ................................................................................................... 291
6.3.5 Real-Time Clock .......................................................................................................... 292
6.3.6 Battery-Backed Memory .............................................................................................. 292
6.3.7 Power Control Using HIB ............................................................................................. 292
6.3.8 Power Control Using VDD3ON Mode ........................................................................... 293
6.3.9 Initiating Hibernate ...................................................................................................... 293
6.3.10 Waking from Hibernate ................................................................................................ 293
6.3.11 Interrupts and Status ................................................................................................... 293
6.4 Initialization and Configuration ..................................................................................... 294
6.4.1 Initialization ................................................................................................................. 294
6.4.2 RTC Match Functionality (No Hibernation) .................................................................... 295
6.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 295
6.4.4 External Wake-Up from Hibernation .............................................................................. 295
6.4.5 RTC or External Wake-Up from Hibernation .................................................................. 295
6.5 Register Map .............................................................................................................. 296
6.6 Register Descriptions .................................................................................................. 296
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7.1
7.2
7.2.1
7.2.2
7.2.3
7.3
7.4
7.5
Internal Memory ................................................................................................... 313
Block Diagram ............................................................................................................ 313
Functional Description ................................................................................................. 313
SRAM ........................................................................................................................ 314
ROM .......................................................................................................................... 314
Flash Memory ............................................................................................................. 316
Register Map .............................................................................................................. 321
Flash Memory Register Descriptions (Flash Control Offset) ............................................ 322
Memory Register Descriptions (System Control Offset) .................................................. 334
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Micro Direct Memory Access (μDMA) ................................................................ 350
8.1 Block Diagram ............................................................................................................ 351
8.2 Functional Description ................................................................................................. 351
8.2.1 Channel Assignments .................................................................................................. 352
8.2.2 Priority ........................................................................................................................ 353
8.2.3 Arbitration Size ............................................................................................................ 353
8.2.4 Request Types ............................................................................................................ 353
8.2.5 Channel Configuration ................................................................................................. 354
8.2.6 Transfer Modes ........................................................................................................... 356
8.2.7 Transfer Size and Increment ........................................................................................ 364
8.2.8 Peripheral Interface ..................................................................................................... 364
8.2.9 Software Request ........................................................................................................ 364
8.2.10 Interrupts and Errors .................................................................................................... 365
8.3 Initialization and Configuration ..................................................................................... 365
8.3.1 Module Initialization ..................................................................................................... 365
8.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 365
October 06, 2012
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