LM3S5R36_13 Datasheet, PDF (932/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Pulse Width Modulator (PWM)
Register 48: PWM0 Generator B Control (PWM0GENB), offset 0x064
Register 49: PWM1 Generator B Control (PWM1GENB), offset 0x0A4
Register 50: PWM2 Generator B Control (PWM2GENB), offset 0x0E4
Register 51: PWM3 Generator B Control (PWM3GENB), offset 0x124
These registers control the generation of the pwmB signal based on the load and zero output pulses
from the counter, as well as the compare A and compare B pulses from the comparators
(PWM0GENB controls the PWM generator 0 block, and so on). When the counter is running in
Count-Down mode, only four of these events occur; when running in Count-Up/Down mode, all six
occur. These events provide great flexibility in the positioning and duty cycle of the resulting PWM
signal.
The PWM0GENB register controls generation of the pwm0B signal; PWM1GENB, the pwm1B
signal; PWM2GENB, the pwm2B signal; and PWM3GENB, the pwm3B signal.
If a zero or load event coincides with a compare A or compare B event, the zero or load action is
taken and the compare A or compare B action is ignored. If a compare A event coincides with a
compare B event, the compare B action is taken and the compare A action is ignored.
If the Generator B update mode is immediate (based on the GENBUPD field encoding in the PWMnCTL
register), the ACTCMPBD, ACTCMPBU, ACTCMPAD, ACTCMPAU, ACTLOAD, and ACTZERO values are
used immediately. If the update mode is locally synchronized, these values are used the next time
the counter reaches zero. If the update mode is globally synchronized, these values are used the
next time the counter reaches zero after a synchronous update has been requested through the
PWM Master Control (PWMCTL) register (see page 888). If this register is rewritten before the
actual update occurs, the previous value is never used and is lost.
PWM0 Generator B Control (PWM0GENB)
PWM0 base: 0x4002.8000
Offset 0x064
Type R/W, reset 0x0000.0000
31
30
29
28
27
26
Type RO
Reset
0
15
Type RO
Reset
0
RO
RO
0
0
14
13
reserved
RO
RO
0
0
RO
RO
RO
0
0
0
12
11
10
ACTCMPBD
RO
R/W
R/W
0
0
0
25
24
23
22
reserved
RO
RO
RO
RO
0
0
0
0
9
8
ACTCMPBU
R/W
R/W
0
0
7
6
ACTCMPAD
R/W
R/W
0
0
21
20
RO
RO
0
0
5
4
ACTCMPAU
R/W
R/W
0
0
19
18
RO
RO
0
0
3
2
ACTLOAD
R/W
R/W
0
0
17
16
RO
RO
0
0
1
0
ACTZERO
R/W
R/W
0
0
Bit/Field
31:12
Name
reserved
Type
RO
Reset Description
0x0000.0
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
932
October 06, 2012
Texas Instruments-Production Data