LM3S5R36_13 Datasheet, PDF (14/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Table of Contents
NRND: Not recommended for new designs.
List of Tables
Table 1.
Table 2.
Table 2-1.
Table 2-2.
Table 2-3.
Table 2-4.
Table 2-5.
Table 2-6.
Table 2-7.
Table 2-8.
Table 2-9.
Table 2-10.
Table 2-11.
Table 2-12.
Table 2-13.
Table 3-1.
Table 3-2.
Table 3-3.
Table 3-4.
Table 3-5.
Table 3-6.
Table 3-7.
Table 3-8.
Table 3-9.
Table 4-1.
Table 4-2.
Table 4-3.
Table 5-1.
Table 5-2.
Table 5-3.
Table 5-4.
Table 5-5.
Table 5-6.
Table 5-7.
Table 5-8.
Table 6-1.
Table 6-2.
Table 6-3.
Table 7-1.
Table 7-2.
Table 7-3.
Table 8-1.
Table 8-2.
Table 8-3.
Table 8-4.
Table 8-5.
Revision History .................................................................................................. 33
Documentation Conventions ................................................................................ 44
Summary of Processor Mode, Privilege Level, and Stack Use ................................ 71
Processor Register Map ....................................................................................... 72
PSR Register Combinations ................................................................................. 77
Memory Map ....................................................................................................... 85
Memory Access Behavior ..................................................................................... 88
SRAM Memory Bit-Banding Regions .................................................................... 90
Peripheral Memory Bit-Banding Regions ............................................................... 90
Exception Types .................................................................................................. 96
Interrupts ............................................................................................................ 96
Exception Return Behavior ................................................................................. 101
Faults ............................................................................................................... 102
Fault Status and Fault Address Registers ............................................................ 103
Cortex-M3 Instruction Summary ......................................................................... 105
Core Peripheral Register Regions ....................................................................... 108
Memory Attributes Summary .............................................................................. 111
TEX, S, C, and B Bit Field Encoding ................................................................... 114
Cache Policy for Memory Attribute Encoding ....................................................... 115
AP Bit Field Encoding ........................................................................................ 115
Memory Region Attributes for Stellaris Microcontrollers ........................................ 115
Peripherals Register Map ................................................................................... 116
Interrupt Priority Levels ...................................................................................... 143
Example SIZE Field Values ................................................................................ 171
JTAG_SWD_SWO Signals (64LQFP) ................................................................. 175
JTAG Port Pins State after Power-On Reset or RST assertion .............................. 176
JTAG Instruction Register Commands ................................................................. 182
System Control & Clocks Signals (64LQFP) ........................................................ 186
Reset Sources ................................................................................................... 187
Clock Source Options ........................................................................................ 194
Possible System Clock Frequencies Using the SYSDIV Field ............................... 197
Examples of Possible System Clock Frequencies Using the SYSDIV2 Field .......... 197
Examples of Possible System Clock Frequencies with DIV400=1 ......................... 198
System Control Register Map ............................................................................. 203
RCC2 Fields that Override RCC Fields ............................................................... 224
Hibernate Signals (64LQFP) ............................................................................... 288
Hibernation Module Clock Operation ................................................................... 294
Hibernation Module Register Map ....................................................................... 296
Flash Memory Protection Policy Combinations .................................................... 317
User-Programmable Flash Memory Resident Registers ....................................... 321
Flash Register Map ............................................................................................ 321
μDMA Channel Assignments .............................................................................. 352
Request Type Support ....................................................................................... 354
Control Structure Memory Map ........................................................................... 355
Channel Control Structure .................................................................................. 355
μDMA Read Example: 8-Bit Peripheral ................................................................ 364
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October 06, 2012
Texas Instruments-Production Data