LM3S5R36_13 Datasheet, PDF (1050/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Register Quick Reference
NRND: Not recommended for new designs.
31
30
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28
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26
25
24
23
22
21
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2
1
0
PWMISC, type R/W1C, offset 0x01C, reset 0x0000.0000 (see page 902)
INTFAULT3 INTFAULT2 INTFAULT1 INTFAULT0
INTPWM3 INTPWM2 INTPWM1 INTPWM0
PWMSTATUS, type RO, offset 0x020, reset 0x0000.0000 (see page 905)
PWMFAULTVAL, type R/W, offset 0x024, reset 0x0000.0000 (see page 907)
FAULT3 FAULT2 FAULT1 FAULT0
PWMENUPD, type R/W, offset 0x028, reset 0x0000.0000 (see page 909)
PWM7 PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 PWM0
ENUPD7
ENUPD6
ENUPD5
ENUPD4
PWM0CTL, type R/W, offset 0x040, reset 0x0000.0000 (see page 913)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
PWM1CTL, type R/W, offset 0x080, reset 0x0000.0000 (see page 913)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
PWM2CTL, type R/W, offset 0x0C0, reset 0x0000.0000 (see page 913)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
PWM3CTL, type R/W, offset 0x100, reset 0x0000.0000 (see page 913)
DBFALLUPD
DBRISEUPD
DBCTLUPD
GENBUPD
PWM0INTEN, type R/W, offset 0x044, reset 0x0000.0000 (see page 918)
ENUPD3
ENUPD2
ENUPD1
ENUPD0
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
GENAUPD
LATCH MINFLTPER FLTSRC
CMPBUPD CMPAUPD LOADUPD DEBUG MODE ENABLE
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
PWM1INTEN, type R/W, offset 0x084, reset 0x0000.0000 (see page 918)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
PWM2INTEN, type R/W, offset 0x0C4, reset 0x0000.0000 (see page 918)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
PWM3INTEN, type R/W, offset 0x104, reset 0x0000.0000 (see page 918)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
TRCMPBD TRCMPBU TRCMPAD TRCMPAU TRCNTLOAD TRCNTZERO
PWM0RIS, type RO, offset 0x048, reset 0x0000.0000 (see page 921)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM1RIS, type RO, offset 0x088, reset 0x0000.0000 (see page 921)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM2RIS, type RO, offset 0x0C8, reset 0x0000.0000 (see page 921)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM3RIS, type RO, offset 0x108, reset 0x0000.0000 (see page 921)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
PWM0ISC, type R/W1C, offset 0x04C, reset 0x0000.0000 (see page 923)
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
INTCMPBD INTCMPBU INTCMPAD INTCMPAU INTCNTLOAD INTCNTZERO
1050
Texas Instruments-Production Data
October 06, 2012