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LM3S5R36_13 Datasheet, PDF (609/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller | |||
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NRND: Not recommended for new designs.
Stellaris® LM3S5R36 Microcontroller
13 Universal Asynchronous Receivers/Transmitters
(UARTs)
The Stellaris® LM3S5R36 controller includes three Universal Asynchronous Receiver/Transmitter
(UART) with the following features:
â Programmable baud-rate generator allowing speeds up to 5 Mbps for regular speed (divide by
16) and 10 Mbps for high speed (divide by 8)
â Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
â Programmable FIFO length, including 1-byte deep operation providing conventional
double-buffered interface
â FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
â Standard asynchronous communication bits for start, stop, and parity
â Line-break generation and detection
â Fully programmable serial interface characteristics
â 5, 6, 7, or 8 data bits
â Even, odd, stick, or no-parity bit generation/detection
â 1 or 2 stop bit generation
â IrDA serial-IR (SIR) encoder/decoder providing
â Programmable use of IrDA Serial Infrared (SIR) or UART input/output
â Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps half-duplex
â Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
â Programmable internal clock generator enabling division of reference clock by 1 to 256 for
low-power mode bit duration
â Support for communication with ISO 7816 smart cards
â LIN protocol support
â Standard FIFO-level and End-of-Transmission interrupts
â Efficient transfers using Micro Direct Memory Access Controller (µDMA)
â Separate channels for transmit and receive
â Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level
â Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
October 06, 2012
609
Texas Instruments-Production Data
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