LM3S5R36_13 Datasheet, PDF (118/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

Cortex-M3 Peripherals
NRND: Not recommended for new designs.
Table 3-7. Peripherals Register Map (continued)
Offset Name
Type
Reset
Description
0xDA4 MPUBASE1
0xDA8 MPUATTR1
0xDAC MPUBASE2
0xDB0 MPUATTR2
0xDB4 MPUBASE3
0xDB8 MPUATTR3
R/W
0x0000.0000 MPU Region Base Address Alias 1
R/W
0x0000.0000 MPU Region Attribute and Size Alias 1
R/W
0x0000.0000 MPU Region Base Address Alias 2
R/W
0x0000.0000 MPU Region Attribute and Size Alias 2
R/W
0x0000.0000 MPU Region Base Address Alias 3
R/W
0x0000.0000 MPU Region Attribute and Size Alias 3
See
page
169
171
169
171
169
171
3.3 System Timer (SysTick) Register Descriptions
This section lists and describes the System Timer registers, in numerical order by address offset.
118
October 06, 2012
Texas Instruments-Production Data