LM3S5R36_13 Datasheet, PDF (204/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

System Control
NRND: Not recommended for new designs.
Table 5-7. System Control Register Map (continued)
Offset Name
Type
Reset
Description
0x120
0x124
0x128
0x144
0x150
0x154
0x190
0x1A0
DCGC0
DCGC1
DCGC2
DSLPCLKCFG
PIOSCCAL
PIOSCSTAT
DC9
NVMSTAT
R/W
0x00000040 Deep Sleep Mode Clock Gating Control Register 0
R/W
0x00000000 Deep-Sleep Mode Clock Gating Control Register 1
R/W
0x00000000 Deep Sleep Mode Clock Gating Control Register 2
R/W
0x0780.0000 Deep Sleep Clock Configuration
R/W
0x0000.0000 Precision Internal Oscillator Calibration
RO
0x0000.0040 Precision Internal Oscillator Statistics
RO
0x00FF.00FF Device Capabilities 9 ADC Digital Comparators
RO
0x0000.0001 Non-Volatile Memory Information
5.5 Register Descriptions
All addresses given are relative to the System Control base address of 0x400F.E000.
See
page
263
271
278
228
230
232
254
256
204
October 06, 2012
Texas Instruments-Production Data