LM3S5R36_13 Datasheet, PDF (643/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Bit/Field
5
4
3:0
Name
TXRIS
RXRIS
reserved
Type
RO
RO
RO
Reset
0
0
0
Description
UART Transmit Raw Interrupt Status
Value Description
1 If the EOT bit in the UARTCTL register is clear, the transmit
FIFO level has passed through the condition defined in the
UARTIFLS register.
If the EOT bit is set, the last bit of all transmitted data and flags
has left the serializer.
0 No interrupt
This bit is cleared by writing a 1 to the TXIC bit in the UARTICR register
or by writing data to the transmit FIFO until it becomes greater than the
trigger level, if the FIFO is enabled, or by writing a single byte if the FIFO
is disabled.
UART Receive Raw Interrupt Status
Value Description
1 The receive FIFO level has passed through the condition defined
in the UARTIFLS register.
0 No interrupt
This bit is cleared by writing a 1 to the RXIC bit in the UARTICR register
or by reading data from the receive FIFO until it becomes less than the
trigger level, if the FIFO is enabled, or by reading a single byte if the
FIFO is disabled.
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
October 06, 2012
643
Texas Instruments-Production Data