LM3S5R36_13 Datasheet, PDF (15/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Table 8-6.
Table 8-7.
Table 8-8.
Table 8-9.
Table 8-10.
Table 8-11.
Table 8-12.
Table 8-13.
Table 9-1.
Table 9-2.
Table 9-3.
Table 9-4.
Table 9-5.
Table 9-6.
Table 9-7.
Table 9-8.
Table 9-9.
Table 9-10.
Table 9-11.
Table 10-1.
Table 10-2.
Table 10-3.
Table 10-4.
Table 10-5.
Table 10-6.
Table 10-7.
Table 10-8.
Table 10-9.
Table 10-10.
Table 11-1.
Table 12-1.
Table 12-2.
Table 12-3.
Table 12-4.
Table 13-1.
Table 13-2.
Table 14-1.
Table 14-2.
Table 15-1.
Table 15-2.
Table 15-3.
Table 15-4.
Table 16-1.
Table 16-2.
Table 16-3.
Table 16-4.
Table 16-5.
μDMA Interrupt Assignments .............................................................................. 365
Channel Control Structure Offsets for Channel 30 ................................................ 366
Channel Control Word Configuration for Memory Transfer Example ...................... 366
Channel Control Structure Offsets for Channel 7 .................................................. 367
Channel Control Word Configuration for Peripheral Transmit Example .................. 368
Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 369
Channel Control Word Configuration for Peripheral Ping-Pong Receive
Example ............................................................................................................ 370
μDMA Register Map .......................................................................................... 371
GPIO Pins With Non-Zero Reset Values .............................................................. 409
GPIO Pins and Alternate Functions (64LQFP) ..................................................... 409
GPIO Pad Configuration Examples ..................................................................... 415
GPIO Interrupt Configuration Example ................................................................ 416
GPIO Pins With Non-Zero Reset Values .............................................................. 417
GPIO Register Map ........................................................................................... 417
GPIO Pins With Non-Zero Reset Values .............................................................. 428
GPIO Pins With Non-Zero Reset Values .............................................................. 434
GPIO Pins With Non-Zero Reset Values .............................................................. 436
GPIO Pins With Non-Zero Reset Values .............................................................. 439
GPIO Pins With Non-Zero Reset Values .............................................................. 445
Available CCP Pins ............................................................................................ 460
General-Purpose Timers Signals (64LQFP) ......................................................... 461
General-Purpose Timer Capabilities .................................................................... 462
Counter Values When the Timer is Enabled in Periodic or One-Shot Modes .......... 463
16-Bit Timer With Prescaler Configurations ......................................................... 464
Counter Values When the Timer is Enabled in RTC Mode .................................... 465
Counter Values When the Timer is Enabled in Input Edge-Count Mode ................. 465
Counter Values When the Timer is Enabled in Input Event-Count Mode ................ 467
Counter Values When the Timer is Enabled in PWM Mode ................................... 468
Timers Register Map .......................................................................................... 473
Watchdog Timers Register Map .......................................................................... 508
ADC Signals (64LQFP) ...................................................................................... 532
Samples and FIFO Depth of Sequencers ............................................................ 533
Differential Sampling Pairs ................................................................................. 540
ADC Register Map ............................................................................................. 549
UART Signals (64LQFP) .................................................................................... 610
UART Register Map ........................................................................................... 619
SSI Signals (64LQFP) ........................................................................................ 667
SSI Register Map .............................................................................................. 678
I2C Signals (64LQFP) ........................................................................................ 708
Examples of I²C Master Timer Period versus Speed Mode ................................... 712
Inter-Integrated Circuit (I²C) Interface Register Map ............................................. 721
Write Field Decoding for I2CMCS[3:0] Field ......................................................... 727
Controller Area Network Signals (64LQFP) .......................................................... 746
Message Object Configurations .......................................................................... 751
CAN Protocol Ranges ........................................................................................ 759
CANBIT Register Values .................................................................................... 759
CAN Register Map ............................................................................................. 763
October 06, 2012
15
Texas Instruments-Production Data