LM3S5R36_13 Datasheet, PDF (35/1063 Pages) Texas Instruments – LM3S5R36 Microcontroller

NRND: Not recommended for new designs.
Stellaris^® LM3S5R36 Microcontroller
Table 1. Revision History (continued)
Date
Revision Description
■ Additional minor data sheet clarifications and corrections.
July 2011
9970
■ Corrected "Reset Sources" table.
■ Added missing PICAL (PIOSC Calibrate) bit to DC4 register.
■ Added Important Note that RCC register must be written before RCC2 register.
■ Added a note that all GPIO signals are 5-V tolerant when configured as inputs except for PB0 and
PB1, which are limited to 3.6 V.
■ Note that the state of the HSE bit in the UARTCTL register has no effect on clock generation in ISO
7816 smart card mode (when the SMART bit in the UARTCTL register is set).
■ Corrected LIN Mode bit names in UART Interrupt Clear (UARTICR) register.
■ The C1+ signal was documented as being on PC5 (pin 14) when it is actually on PC7 (pin 16). All
pin tables have been corrected.
■ Corrected pin number for RST in table "Connections for Unused Signals" (other pin tables were
correct).
■ In the "Operating Characteristics" chapter:
– In the "Thermal Characteristics" table, the Thermal resistance value was changed.
– In the "ESD Absolute Maximum Ratings" table, the V_ESDCDM parameter was changed and the
V_ESDMM parameter was deleted.
■ The "Electrical Characteristics" chapter was reorganized by module. In addition, some of the
Recommended DC Operating Conditions, LDO Regulator, Clock, GPIO, Hibernation Module, ADC,
and SSI characteristics were finalized.
■ Added missing ordering table.
■ Additional minor data sheet clarifications and corrections.
October 06, 2012
35
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